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ST24E16

16 Kbit Serial I2C EEPROM with Extended Addressing

STMicroelectronics 

ST24E16, ST25E16

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus, fC = 400kHz

20

VCC

16

12

8

4

VCC = 5V

SDA

MASTER SCL

RL

RL

CBUS

CBUS

0

25

50

75

100

CBUS (pF)

AI01115

DEVICE OPERATION

I2C Bus Background

The ST24/25E16 support the extended addressing

I2C protocol. This protocol defines any device that

sends data onto the bus as a transmitter and any

device that reads the data as a receiver.The device

that controls the data transfer is known as the

master and the other as the slave. The master will

always initiate a data transfer and will provide the

serial clock for synchronisation. The ST24/25E16

are always slave devices in all communications.

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the ST24/25E16 con-

tinuously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the ST24/25E16

and the bus master. A STOP condition at the end

of a Read command forces the standby state. A

STOP condition at the end of a Write command

triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successful data transfer. The

bus transmitter, either master or slave, will release

the SDA bus after sending 8 bits of data. During the

9th clock pulse the receiver pulls the SDA bus low

to acknowledge the receipt of the 8 bits of data.

Data Input. During data input the ST24/25E16

sample the SDA bus signal on the rising edge of

the clock SCL. For correct device operation the

SDA signal must be stable during the clock low to

high transition and the data must change ONLY

when the SCL line is low.

Device Selection. To start communication be-

tween the bus master and the slave ST24/25E16,

the master must initiate a START condition. The 8

bits sent after a START condition are made up of a

device select of 4 bits that identifies the device type,

3 Chip Enable bits and one bit for a READ (RW =

1) or WRITE (RW = 0) operation. There are two

modes both for read and write. These are summa-

rised in Table 4 and described hereafter. A commu-

nication between the master and the slave is ended

with a STOP condition.

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