AMD
General Information
1.4
Pin Functions
The SCC pins are divided into seven functional groups: Address/Data, Bus Timing and
Reset, Device Control, Interrupt, Serial Data (both channels), Peripheral Control (both
channels), and Clocks (both Channels). Figures 1–3 and 1–4 show the pins in each func-
tional group for the 40- and 44-pin SCC versions.
The Address/Data group consists of the bidirectional lines used to transfer data between
the CPU and the SCC. The direction of these lines depends on whether the SCC is se-
lected and whether the operation is a Read or a Write.
The Timing and Control groups designate the type of transaction to occur and when this
transaction will occur. The Interrupt group provides inputs and outputs to conform to the
Z-Bus specifications for handling and prioritizing interrupts. The remaining groups are di-
vided into Channel A and Channel B groups for serial data (transmit or receive), peripher-
al control (such as DMA or Modem), and the input and output lines for the receive and
transmit clocks.
Data
Bus
8
Bus
Timing
and Reset
Control
Interrupt
D0 - D7
RD
WR
A/B
CE
D/C
INT
INTACK
IEI
IEO
Am85C30/
Am8530H
SCC
TxDA
RxDA
TRxCA
RTxCA
SYNCA
W/REQA
DTR / REQA
RTSA
CTSA
DCDA
TxDB
RxDB
TRxCB
RTxCB
SYNCB
W/REQB
DTR/REQB
RTSB
CTSB
DCDB
Serial
Data
Channel
Clocks
Channel
Controls
for Modem,
DMA, or
Other
Serial
Data
Channel
Clocks
Channel
Controls
for Modem,
DMA, or
Other
+5 V
GND PCLK
Figure 1–3. SCC Pin Functions
10216A-004A
1–6