AM85C30(1992) Ver la hoja de datos (PDF) - Advanced Micro Devices

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AM85C30
(Rev.:1992)

Serial Communications Controller

Advanced Micro Devices 

AMD

General Information

s Asynchronous capabilities:

– 5, 6, 7, or 8 bits per character

– 1, 1-1/2, or 2 stop bits

– Odd or Even Parity

– x1, 16, 32, or 64 clock modes

– Break generation and detection

– Parity, Overrun and Framing Error detection

s Character-Oriented synchronous capabilities:

– Internal or external character synchronization

– 1 or 2 sync characters in separate registers

– Automatic CRC generation/detection

s SDLC/HLDC capabilities:

– Abort sequence generation and checking

– Automatic zero bit insertion and deletion

– Automatic flag insertion between messages

– Address field recognition

– I-Field residue handling

– CRC generation/detection

– SDLC Loop mode with EOP recognition/loop entry and exit

s Receiver data registers quadruply buffered. Transmitter data register doubly buffered

s NRZ, NRZI, or FM encoding/decoding and Manchester decoding

s Baud-rate generator in each channel

s A DPLL in each channel for clock recovery

s Crystal oscillator in each channel

s Local Loopback and Auto Echo modes

In addition, the Am85C30 provides enhancements which allow it to be used more effec-

tively in high speed SDLC/HDLC applications. These enhancements include:

– 10 x 19-bit SDLC/HDLC frame status FIFO

– 14-bit SDLC/HDLC frame byte counter

– Automatic SDLC/HDLC opening Flag transmission

– Automatic SDLC/HDLC Tx Underrun/EOM Flag reset

– Automatic SDLC/HDLC CRC generator preset

– TxD forced High in SDLC NRZI mode when in mark idle

– RTS synchronization to closing SDLC/HDLC Flag

– DTR/REQ DMA request deactivation delay reduced

– External PCLK to RTxC or TRxC synchronization requirement removed for one fourth

PCLK operation

– Reduced Interrupt response time

– Reduced Read/Write access recovery time (Trc) to 3 PCLK best case (3 1/2 PCLK

worst case)

– Improved WAIT timing

Other enhancements which make the Am85C30 more user friendly include:

– Write data valid setup time to negative edge of write strobe requirement eliminated

– Write Registers WR3, WR4, WR5, WR10 and WR7′ are readable

– Complete reception of SDLC/HDLC CRC characters

– Lower priority interrupt masking without INTACK generation

1–4

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