AS1700-NPN Ver la hoja de datos (PDF) - Astec Semiconductor => Silicon Link
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AS1700-NPN Datasheet PDF : 20 Pages
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AS17xx
Semicustom Bipolar Array
Features
Size (single tile)
• 87 x 75 mils
Expandability of array
(to 2 or 4 tiles)
Component Availability
(single tile)
• Small NPN
• Dual collector PNP
• Vertical PNP
• Power NPN
• Diffused Resistors
(total)
• Pinch Resistors
(3-terminal, 30kΩ)
• Cross-unders
• Buses
48
21
4
3
≈300 kΩ
8
13
6
Basic Electrical Specs
• Transistor Matching
(NPN & PNP)
<2%
• Primary voltage limitations:
LVCEO
18 V
BVCBO
30 V
• Diffusion to substrate
(Ground)
30 V
• NPN Parameters
Beta
80–500
fT (1mA)
BVEBO
300 MHz
7V
• PNP Parameters:
Beta
20–300
fT (1mA)
BVEBO
300 MHz
30 V
Description
The AS17xx is Astec’s proprietary semicustom bipolar array.
This semicustom IC is a collection of individual transistors
and resistors in a fixed configuration. The custom circuit is
manufactured by creating a single metal mask to connect the
components. This allows the designer to deal with only one
mask for the IC layout instead of the actual 10 mask process.
The semicustom array is useful for a wide range of functions,
both analog and digital. In its simplest configuration, the
AS17xx has 76 active devices available, but can be ex-
panded to give up to four times this number in its largest
configuration. This expandability of the array is a unique
feature, allowing a whole range of semicustom circuits to be
manufactured.
Because Astec has ongoing manufacturing of high volume
circuits on this array, incremental wafer costs for engineering
purposes are low. Therefore quality and reliability can be
maintained even with small volume or engineering lots.
Since the silicon can be completely processed and held
awaiting only the metal etch and passivation steps, ex-
tremely fast turn-around times can be achieved.
The AS17xx bipolar array uses a standard “20 Volt” bipolar
technology. Although quite similar to industry standard ar-
rays, it has a number of important improvements. First, the
ratio of PNPs to NPNs has been increased to allow for more
modern design practice. Second, the process has been
modified to allow for a deep collector diffusion (sinker) which
not only improves the VCE(SAT) of the transistors, but also
allows for the elimination of regions with thin oxide which
historically plague semicustom die with electrostatic dis-
charge reliability concerns. Third, a set of low resistance
sinker resistors allows for bussing supply or signal lines
without using active components for cross-unders. In addi-
tion, the specific component geometries have been further
optimized to facilitate the layout compared to the industry
standard arrays. Resistors are now in a binary weighted
500 / 1k / 2k / 4k sequence for more simple value calcula-
tions. The power devices use multiple standard size emitters
© ASTEC Semiconductor
119
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