IS61SP12832 Ver la hoja de datos (PDF) - Integrated Silicon Solution
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IS61SP12832 Datasheet PDF : 15 Pages
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IS61SP12832
IS61SP12836
ISSI ®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
fMAX(3)
tKC(3)
tKH
tKL(3)
tKQ(3)
tKQX(1)
tKQLZ(1,2)
tKQHZ(1,2)
tOEQ(3)
tOEQX(1)
tOELZ(1,2)
tOEHZ(1,2)
tAS(3)
tSS(3)
tWS(3)
tCES(3)
tAVS(3)
tAH(3)
tSH(3)
tWH(3)
tCEH(3)
tAVH(3)
-200
-166
-150
-133
-5
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock Frequency
— 200
— 166
— 150
— 133
— 100 MHz
Cycle Time
5—
6—
6.7 —
7.5 —
10 —
ns
Clock High Time
2.3 —
2.4 —
2.6 —
2.8 —
3—
ns
Clock Low Time
2.3 —
2.4 —
2.6 —
2.8 —
3—
ns
Clock Access Time
— 3.1
— 3.5
— 3.8
—4
—5
ns
Clock High to Output Invalid
3—
3—
3—
3—
3—
ns
Clock High to Output Low-Z
0—
0—
0—
0—
0—
ns
Clock High to Output High-Z
1.5 3.5
1.5 3.5
1.5 3.5
1.5 3.5
1.5 3.5
ns
Output Enable to Output Valid — 3.1
— 3.5
— 3.5
— 3.8
—5
ns
Output Disable to Output Invalid 0 —
0—
0—
0—
0—
ns
Output Enable to Output Low-Z 0 —
0—
0—
0—
0—
ns
Output Disable to Output High-Z 2 3
2 3.5
2 3.5
2 3.8
25
ns
Address Setup Time
1.5 —
1.5 —
1.5 —
1.5 —
2—
ns
Address Status Setup Time
1.5 —
1.5 —
1.5 —
1.5 —
2—
ns
Write Setup Time
1.5 —
1.5 —
1.5 —
1.5 —
2—
ns
Chip Enable Setup Time
1.5 —
1.5 —
1.5 —
1.5 —
2—
ns
Address Advance Setup Time 1.5 —
1.5 —
1.5 —
1.5 —
2—
ns
Address Hold Time
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
ns
Address Status Hold Time
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
ns
Write Hold Time
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
ns
Chip Enable Hold Time
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
ns
Address Advance Hold Time
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
PRELIMINARY INFORMATION Rev. 00B
04/04/00
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