IS61LF12836-8.5BI Ver la hoja de datos (PDF) - Integrated Silicon Solution

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Fabricante

IS61LF12836-8.5BI

128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM

Integrated Silicon Solution 

IS61LF12832

IS61LF12836

ISSI ®

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

Symbol

Parameter

7.5

Min.

Max.

fMAX(3)

Clock Frequency

—

113

tKC(3)

Cycle Time

8.8

—

tKH

Clock High Time

2.5

—

tKL(3)

Clock Low Time

2.5

—

tKQ(3)

Clock Access Time

—

7.5

tKQX(1)

Clock High to Output Invalid

1.5

—

tKQLZ(1,2)

Clock High to Output Low-Z

0

—

tKQHZ(1,2)

Clock High to Output High-Z

2

3.5

tOEQ(3)

Output Enable to Output Valid

—

3.5

tOELZ(1,2)

Output Enable to Output Low-Z

0

—

tOEHZ(1,2)

Output Disable to Output High-Z

—

3.5

tAS(3)

Address Setup Time

1.5

—

tSS(3)

Address Status Setup Time

1.5

—

tWS(3)

Write Setup Time

1.5

—

tCES(3)

Chip Enable Setup Time

1.5

—

tAVS(3)

Address Advance Setup Time

1.5

—

tAH(3)

Address Hold Time

0.5

—

tSH(3)

Address Status Hold Time

0.5

—

tWH(3)

Write Hold Time

0.5

—

tCEH(3)

Chip Enable Hold Time

0.5

—

tAVH(3)

Address Advance Hold Time

0.5

—

Notes:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

3. Tested with load in Figure 1.

8.5

Min.

Max.

—

100

10

—

3.0

—

3.0

—

—

8.5

3

—

0

—

2

3.5

—

3.5

0

—

—

3.5

1.8

—

1.8

—

1.8

—

1.8

—

1.8

—

0.5

—

0.5

—

0.5

—

0.5

—

0.5

—

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Integrated Silicon Solution, Inc. — 1-800-379-4774

9

PRELIMINARY INFORMATION Rev. 00A

05/28/2001

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