GLT44032-E-35 Ver la hoja de datos (PDF) - G-Link Technology
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componentes Descripción
Fabricante
GLT44032-E-35 Datasheet PDF : 12 Pages
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GLT44032-E
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CA[7:0]
RA[8:0]
RAS
WE Clock
Generator
CAS Clock
Generator
Column
Address
Buffers
Refresh
Counter &
Controller
Row
Address
Buffers
RAS Clock
Generator
OE Clock
Generator
AY[7:0]
Column Decoders
Sense Amplifiers
256 x 32
AX[8:0]
512
Memory Array
512 x 256 x 32
Data RW
Control
Data I/O
DO[31:0]
DI[31:0]
Figure 1. GLT44032-E - 128K x 32
Pin Descriptions
Symbol
Type
Description
DI[31:0]
Input Data input.
DO[31:0]
Output Data output.
RA[8:0]
Input Row address.
CA[7:0]
Input Column address.
RAS
Input Row address strobe.
CAS
Input Column address strobe.
WE
Input Write enable.
OE
Input Output enable.
DQM[3:0]
VCC [1]
VSS [1]
I/O
Supply
Supply
Data-in mask (active low)
3.3v voltage supply, 4 pairs double bond minimum
Ground (voltage return), 4 pairs double bond minimum
1. VCC and VSS for the EmDRAM should be separated from the Logic portion of the chip.
2
G-LINK Technology
May 1997 (Rev. 1)
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