MXED202 Ver la hoja de datos (PDF) - Clare Inc => IXYS

Número de pieza

componentes Descripción

Fabricante

MXED202

128-Channel OLED Row Driver

Clare Inc => IXYS 

MXED202

Preliminary

Pin List (Continued)

ROPT

[Pages 10-11]

I/O/A

RSTB

I

R(n)

O

HREF

O

LREF

O

NRMH

O

NRML

O

Resistor OPTion pin, normally N/C for digitally controlled precharge timing (PCB),

or when precharge is disabled. When a resistor R is connected between ROPT

and PCB, and a capacitor C is connected between PCB and VSS, the precharge

time will be RC/1.65 when measured from the rising edge of CLK to the falling

edge of ROPT. The timing components should be selected such that RC/1.65 not

exceed 10% of the row active time.

ReSeT Bar, static, active low reset input, clears all the shift register cells, elimi

nating token content.

Row driver outputs. R(0)-R(127) are used in 128 output mode, S128=1. Only

R(4)-R(123) should be connected when S128=0.

High voltage REFerence is an internally generated PFET switch drive voltage

(approximately five-volts less than VOH), which should be bypassed to VOH with

a 2200pF external capacitor.

Low voltage REFerence is an internally generated NFET switch drive voltage

(approximately five-volts above GND), which should be bypassed to GND with a

2200pF external capacitor.

Test Pin, N/C

Test Pin, N/C

ELECTRICAL SPECIFICATION

Note: positive currents flow into the part, negative currents flow out of the part.

Absolute Maximum Ratings:

Parameter

Ambient temp

Low voltage supply

High voltage supply

Operating Condition

-

-

-

Min

Typ Max

Units

-65

155

oC

-0.3

7.0

V

-0.3

35.0

V

Operating Conditions:

Unless otherwise stated, all parameters are specified for the following operating conditions.

Parameter

Ambient temp

Low voltage supply

High voltage supplies

Clock Frequency

Sym

TA

VCC

VMAX

CLK

Operating Condition

-

-

-

-

Min

0

3.0

5.0

-

Typ Max

-

70

-

5.5

-

30

-

100

Units

oC

V

V

kHz

6

www.clare.com

Rev. 2

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