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UT1553B_

RTR Remote Terminal with RAM

Aeroflex UTMC 

1.0 ARCHITECTURE AND OPERATION

The UT1553B RTR is an interface device linking a MIL-

STD-1553 serial data bus and a host microprocessor system.

The RTR’s MIL-STD-1553B interface includes encoding/

decoding logic, error detection, command recognition, 1K

x 16 of SRAM, pointer registers, clock, and reset circuits.

1.1 Memory Map and Host Memory Interface

The host can access the 1K x 16 RAM memory like a

standard RAM device through the 10-bit address and 16-bit

data buses. The host uses the Chip Select (CS), Read/Write

(RD/WR), and Output Enable (OE) signals to control data

transfer to and from memory. When the RTR requires access

to its own internal RAM, it asserts the RBUSY signal to

alert the host. The RBUSY signal is programmable via the

internal Control Register to be asserted either 5.7ms or

2.7ms prior to the RTR needing access to its internal RAM.

The RTR stores MIL-STD-1553B messages in 1K x 16 of

on-chip RAM. For efficient use of the 1K x 16 memory on

the RTR, the host programs a set of pointers to map where

the 1553B message is stored. The RTR uses the upper 64

words (address 3C0 (hex) through 3FF (hex)) as pointers.

The RTR provides pointers for all 30 receive subaddresses,

all 30 transmit subaddresses, and four mode code

commands with associated data words as defined in MIL-

STD-1553B. The remaining 960 words of memory

contain receive, transmit, and mode code data in a

host-defined structure.

Message

Storage

Locations

RTR Memory Map

000 (hex)

15 MSB

0 LSB

Receive

Message

Pointers

(3C1 TO 3DE)

XMIT VECTOR WORD MODE CODE (W/DATA)

RCV SUBADDRESS 01

RCV SUBADDRESS 30

SYNCHRONIZE MODE CODE (W/DATA)

15 MSB

0 LSB

Transmit

Message

Pointers

(3E1 TO 3FE)

XMIT LAST COMMAND MODE CODE (W/DATA)

XMT SUBADDRESS 01

15 MSB

XMT SUBADDRESS 30

XMT BIT WORD MODE CODE (W/DATA)

Figure 2. RTR Memory Map

0 LSB

3BF(hex)

3C0 (hex)

3C1 (hex)

3DE (hex)

3DF (hex)

3E0 (hex)

3E1 (hex)

3FE (hex)

3FF (hex)

RTR-3

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