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5962R9582101VQC

Radiation Hardened CMOS High Performance Programmable DMA Controller

Intersil 

HS-82C37ARH

instruction. The adjacent table lists the function of the

command bits. See Figure 10 for Read and Write addresses.

Command Register

76543210

BIT NUMBER

0 MEM-TO-MEM DISABLE

1 MEM-TO-MEM ENABLE

0 CH. 0 ADDR. HOLD DISABLE

1 CH. 0 ADDR. HOLD ENABLE

X IF BIT 0 = 0

0 CONTROLLER ENABLE

1 CONTROLLER DISABLE

0 NORMAL TIMING

1 COMPRESSED TIMING

X IF BIT 0 = 1

0 FIXED PRIORITY

1 ROTATING PRIORITY

0 LATE WRITE SELECTION

1 EXTENDED WRITE SEL.

X IF BIT 3 = 1

0 DREQ SENSE ACTIVE HIGH

1 DREQ SENSE ACTIVE LOW

0 DACK SENSE ACTIVE LOW

1 DACK SENSE ACTIVE HIGH

Status Register - The Status Register contains information

about the present status of the HS-82C37ARH and can be

read by the microprocessor. This information includes which

channels have reached a terminal count and which channels

have pending DMA requests. Bits 0-3 are set every time a

TC is reached by that channel or an external EOP is applied.

These bits are cleared upon Reset, Master Clear, and on

each Status Read. Bits 4-7 are set whenever their

corresponding channel is requesting service, regardless of

the mask bit state. If the mask bits are set, software can poll

the Status Register to determine which channels have

DREQs, and selectively clear a mask bit, thus allowing user

defined service priority. Status bits 4-7 are updated while the

clock is high, and latched on the falling edge. Status Bits 4-7

are cleared upon Reset or Master Clear.

Status Register

76543210

BIT NUMBER

1 CHANNEL 0 HAS REACHED TC

1 CHANNEL 1 HAS REACHED TC

1 CHANNEL 2 HAS REACHED TC

1 CHANNEL 3 HAS REACHED TC

1 CHANNEL 0 REQUEST

1 CHANNEL 1 REQUEST

1 CHANNEL 2 REQUEST

1 CHANNEL 3 REQUEST

Temporary Register - The Temporary Register is used to

hold data during Memory-to-Memory transfers. Following the

completion of the transfer, the last word moved can be read

by the microprocessor by accessing this register. The

Temporary Register always contains the last byte transferred

in the previous Memory-to-Memory operation, unless

cleared by a Reset or Master Clear.

OPERATION

A3

A2

A1

A0

IOR

IOW

Read Status Register

1

0

0

0

0

1

Write Command Register

1

0

0

0

1

0

Read Request Register

1

0

0

1

0

1

Write Request Register

1

0

0

1

1

0

Read Command Register

1

0

1

0

0

1

Write Single Mask Bit

1

0

1

0

1

0

Read Mode Register

1

0

1

1

0

1

Write Mode Register

1

0

1

1

1

0

Set Byte Pointer F/F

1

1

0

0

0

1

Clear Byte Pointer F/F

1

1

0

0

1

0

Read Temporary Register

1

1

0

1

0

1

Master Clear

1

1

0

1

1

0

Clear Mode Reg. Counter

1

1

1

0

0

1

Clear Mask Register

1

1

1

0

1

0

Read All Mask Bits

1

1

1

1

0

1

Write All Mask Bits

1

1

1

1

1

0

FIGURE 10. SOFTWARE COMMAND CODES AND REGISTER CODES

17

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