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5962R9582101VQC

Radiation Hardened CMOS High Performance Programmable DMA Controller

Intersil 

HS-82C37ARH

The HS-82C37ARH may be programmed with the clock

stopped, provided that HLDA is low and at least one rising

clock edge has occurred after HLDA was driven low, so the

controller is in an SI state. Address lines A0-A3 are inputs to

the device and select which registers will be read or written.

The IOR and IOW lines are used to select and time the read

or write operations. Due to the number and size of the internal

registers, an internal flip-flop is used to generate an additional

bit of address. The bit is used to determine the upper or lower

byte of the 16-bit Address and Word Count Registers. The

flip-flop is reset by Master Clear or Reset. Separate software

commands can also set or reset this flip-flop.

Special software commands can be executed by the

HS-82C37ARH in the Program Condition. These commands

are decoded as sets of addresses with CS, IOR, and IOW.

The commands do not make use of the data bus.

Instructions include Set and Clear First/Last Flip-Flop,

Master Clear, Clear Mode Register Counter, and Clear Mask

Register.

Active Cycle

When the HS-82C37ARH is in the Idle cycle, and a software

request or an unmasked channel requests a DMA service,

the device will output an HRQ to the microprocessor and

enter the Active cycle. It is in this cycle that the DMA service

will take place, in one of four modes:

Single Transfer Mode - In Single Transfer mode, the device

is programmed to make one transfer only. The word count

will be decremented and the address decremented or

incremented following each transfer. When the word count

“rolls over” from zero to FFFFH, a terminal count (TC) bit in

the Status Register is set, an EOP pulse is generated, and

the channel will Autoinitialize if this option has been

selected. If not programmed to Autoinitialize, the mask bit

will be set, along with the TC bit and EOP pulse.

DREQ must be held active until DACK becomes active. If

DREQ is held active throughout the single transfer (there-by

triggering a second transfer), HRQ will still go inactive and

release the bus to the system. Then it will again go active

and, upon receipt of a new HLDA, another single transfer will

be performed, unless a higher priority channel takes over. In

HS-80C85RH or HS-80C86RH systems, this will ensure one

full machine cycle execution between DMA transfers. Details

of timing between the HS-82C37ARH and other bus control

protocols will depend upon the characteristics of the

microprocessor involved.

Block Transfer Mode - In Block Transfer Mode, the device is

activated by DREQ or software request and continues

making transfers during the service until a TC, caused by

word count going to FFFFH, or an external End of Process

(EOP) is encountered. DREQ need only beheld active until

DACK becomes active. Again, an Autoinitialization will occur

at the end of the service if the channel has been

programmed for that option.

Demand Transfer Mode - In Demand Transfer Mode the

device continues making transfers until a TC or external

EOP is encountered, or until DREQ goes inactive. Thus,

transfers may continue until the I/O device has exhaust edits

data capacity. After the I/O device has had a chance to catch

up, the DMA service is reestablished by means of a DREQ.

During the time between services when the micro-processor

is allowed to operate, the intermediate values of address and

word count are stored in the HS-82C37ARH Current

Address and Current Word Count Registers. Higher priority

channels may intervene in the demand process, once DREQ

has gone inactive. Only an EOP can cause an

Autoinitialization at the end of the service. EOP is generated

either by TC or by an external signal.

Cascade Mode - This mode is used to cascade more than

one HS-82C37ARH for simple system expansion. The HRQ

and HLDA signals from the additional HS-82C37ARH are

connected to the DREQ and DACK signals respectively of a

channel for the initial HS-82C37ARH. This allows the DMA

requests of the additional device to propagate through the

priority network circuitry of the preceding device. The priority

chain is preserved and the new device must wait for its turn

to acknowledge requests. Since the cascade channel of the

initial HS-82C37ARH is used only for prioritizing the

additional device, it does not output an address or control

signals of its own so that there is no conflict with the

cascaded device. The HS-82C37ARH will respond to DREQ

and generate DACK but all other outputs except HRQ will be

disabled. An external EOP will be ignored by the initial

device, but will have the usual effect on the added device.

Figure 9 shows two additional devices cascaded with an

initial device using two of the previous channels. This forms

a two-level DMA system. More HS-82C37ARHs could be

added at the second level by using the remaining channels

of the first level. Additional devices can also be added by

cascading into the channels of the second level devices,

forming a third level.

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