MAQ9264C70CB Ver la hoja de datos (PDF) - Dynex Semiconductor

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MAQ9264C70CB

Radiation hard 8192 x 8 bit static RAM

Dynex Semiconductor 

MA9264

ADDRESS

WE

TAVWL

DATA OUT

(8)

HIGH

IMPEDANCE

DATA IN

CS

CE

TAVAVW

TAVWH

TWLWH (2)

(4)

TWLQZ

(5)

TWHAV (3)

TAXQX

TWLQX

(6)

(7)

TSLWH

TDVWH

DATA VALID

TWHDX

TEHWH

1. WE must be high during all address transitions.

2. A write occurs during the overlap (TWLWH) of a low CS, a high CE and a low WE.

3. TWHAV is measured from either CS or WE going high or CE going low, whichever is the earlier, to the end

of the write cycle.

4. If the CS low or CE high transition occurs simultaneously with, or after, the WE low transition, the output

remains in the high impedance state.

5. DATA OUT is in the active state, so DATA IN must not be in the opposing state.

6. DATA OUT is the write data of the current cycle, if selected.

7. DATA OUT is the read data of the next address,if selected.

8. OE is low. (If OE is high then DATA OUT remains in the high impedance state throughout the cycle).

Figure 12: Write Cycle

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