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MC100E116FN

5V ECL Quint Differential Line Receiver

ON Semiconductor 

MC10E116, MC100E116

5V ECL Quint Differential

Line Receiver

Description

The MC10E/100E116 is a quint differential line receiver with

emitter-follower outputs. For applications which require bandwidths

greater than that of the E116, the E416 device may be of interest.

Active current sources plus a deep collector feature of the MOSAIC

III process provide the receivers with excellent common-mode noise

rejection. Each receiver has a dedicated VCCO supply lead, providing

optimum symmetry and stability.

If both inverting and non-inverting inputs are at an equal potential of

> −2.5 V, the receiver does not go to a defined state, but rather

current-shares in normal differential amplifier fashion, producing

output voltage levels midway between HIGH and LOW, or the device

may even oscillate.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Features

• 500 ps Max. Propagation Delay

• VBB Supply Output

• Dedicated VCCO Pin for Each Receiver

• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V

with VEE = −4.2 V to −5.7 V

• Output Qs will default low when inputs are < VCC −2.5 V

• Internal Input 50 kW Pulldown Resistors

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• ESD Protection: Human Body Model; > 2 kV,

Machine Model; > 200 V

• Moisture Sensitivity Level:

Pb = 1

Pb−Free = 3

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 98 devices

• Pb−Free Packages are Available*

http://onsemi.com

PLCC−28

FN SUFFIX

CASE 776

MARKING DIAGRAM*

1

MCxxxE116G

AWLYYWW

xxx = 10 or 100

A

= Assembly Location

WL = Wafer Lot

YY

= Year

WW = Work Week

G

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2006

1

November, 2006 − Rev. 10

Publication Order Number:

MC10E116/D

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