XE1212C Ver la hoja de datos (PDF) - Xecom
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XE1212C Datasheet PDF : 16 Pages
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UART Register Function Summary
Register Address
0
0
1
2
3
4
5
(DLAB=0)
(DLAB=0) (DLAB=0)
6
0
1
(DLAB=1) (DLAB=1)
Receiver
Bit
Buffer
No. Register
(RBR)
Transmitter
Holding
Register
(THR)
Interrupt
Enable
Register
(IER)
Interrupt
Indent.
Register
(IIR)
Line
Control
Register
(LCR)
Modem
Control
Register
(MCR)
Line
Status
Register
(LSR)
Modem
Status
Register
(MSR)
Divisor
Latch
(DLL)
Divisor
Latch
(DLM)
0
Data Bit
0*
1
Data Bit
1
2
Data Bit
2
3
Data Bit
3
Data Bit
0*
Data Bit
1
Data Bit
2
Data Bit
3
Enable
RXD
Available
Interrupt
Enable
Transmitter
Holding
Reg. Empty
Interrupt
Enable
Receiver
Line Status
Interrupt
Enable
Modem
Status
Interrupt
"0" if
Interrupt
Pending
Word Length
Selection
Bit 0
Data
Terminal
Ready
(DTR)
Data
Ready
Interrupt
Ident.
Bit 0
Word Length
Selection
Bit 1
Request
to Send
(RTS)
Overrun
Error
(OE)
Interrupt
Ident.
Bit 1
0
Stop Bits
0=1 SB
1=2 SB
Parity
Enable
1=PEN
Output 1
Parity
Error
(PE)
Framing
Output 2 Error
(FE)
Delta
CTS
Delta
DSR
Trailing
Edge
Ring
Indicator
Delta
Rx Line
Signal
Detect
Bit 0
Bit 1
Bit 2
Bit 3
Bit 8
Bit 9
Bit 10
Bit 11
4
Data Bit
Data Bit
0
4
4
0
Even Parity
Local
Break
Clear to
Bit 4
Select
Loopback Interrupt
Send
1=EPS
(CTS)
Bit 12
5
Data Bit
Data Bit
0
5
5
6
Data Bit
Data Bit
0
6
6
7
Data Bit
Data Bit
0
7
7
Stick
Transmit
0
Parity
0
Holding Data Set
Bit 5
Bit 13
1=SP
Register Ready
Empty
(DSR)
(THRE)
Transmit
Set
Shift
Ring
0
Break
0
Register Indicator
Bit 6
Bit 14
1=SB
Empty
(RI)
(TSRE)
Divisor
Received
Latch
Line
0
Access
0
0
Signal
Bit 7
Bit 15
Bit
Detect
(DLAB)
*Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
XECOM
(5)
XE1212C
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