XE1212C Ver la hoja de datos (PDF) - Xecom
Número de pieza
componentes Descripción
Fabricante
XE1212C Datasheet PDF : 16 Pages
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Mechanical Specifications
Inches
Min Max
A 2.255 2.305
B 0.985 1.015
C 0.490 0.510
D 0.890 0.910
E 1.890 1.910
F 0.125 0.200
G 0.040 0.060
H 0.180 0.200
J 0.090 0.110
Milimeters
Min Max
57.2 58.6
25.0 25.8
12.4 13.0
22.6 23.1
48.0 48.5
3.1 5.1
1.0 1.5
4.5 5.1
2.3 2.8
Pins = 0.020" X 0.014"
All pins tin-plated
Recommended hole size = 0.045"
Pin Descriptions
PIN NAME
DESCRIPTION
1
N/C
2
GND
3
VCC
4
\RI
5,6,7,8
N/C
9
OH
10,11
12
N/C
AUDIO
13
INT
14-16 A0..A2
No Connect.
Ground Reference (0 volts).
Positive Supply Voltage (+5 volts).
Ring Indication. A low level on this status line indicates the presence of the ring cycle on
Tip and Ring. This line is normally used for test/status only.
No Connect
This signal allows the user to monitor the status of the hookswitch relay in the XE1212C.
When the signal on OH is high, the relay is closed, and the XE1212Csiezes the telephone
line. During rotary dialing, this line is pulsed at a rate of 10 pulses per second.
No Connect
A programmable attenuator that can drive a load impedance of 300 ohms is provided on
this pin to allow monitoring of the telephone line signal through an external speaker. The L
and M commands adjust speaker volume and control when the audio signal will be
presented. The Audio Output in conjunction with an external audio amplifier (such as an
LM386) can drive a low impedance speaker.
The Interrupt Line goes high whenever any of the enabled interrupts in the Interrupt Enable
Register (IER) is active. The interrupts are Received Data Available, Transmitter Holding
Register Empty, Receiver Line Status and Modem Status. The Interrupt Line is reset upon
the appropriate interrupt servicing. This pin is forced to a Hi-Z state when bit 3 bit of the
modem control register (MCR) is low (power on state).
These 3 address inputs select a UART register during read or write operations as shown in
Table 1. The Divisor Latch Access Bit (DLAB) of the LCR register must be set high by the
system software to access the bit rate Divisor Latch (DLM) as shown in Table 2.
XECOM
(2)
XE1212C
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