AD1843 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD1843 Datasheet PDF : 64 Pages
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AD1843
Miscellaneous
Pin Name PQFP
XTALI
61
TQFP
76
XTALO 62
77
PWRDWN 51
64
RESET 52
65
PDMNFT 49
61
CMOUT 38
47
VREF
39
48
FILTL
25
31
FILTR
23
29
AAFILTL 24
30
AAFILTR 22
28
I/O Description
I 24.576 MHz Crystal Input. When using a crystal as the clock source, the crystal
should be connected between the XTALI and XTALO pins. This crystal should
be 24.576 MHz for the normal sampling rate range, i.e., 4 kHz to 54 kHz. A
clock input (perhaps the CLKOUT of another AD1843) may be driven into
XTALI in place of a crystal. The external clock input must be greater than or equal
to 512 times the maximum desired AD1843 sampling frequency.
O 24.576 MHz Crystal Output. When using a crystal as the clock source, the crystal
should be connected between the XTALI and XTALO pins. If a clock is driven
directly into XTALI, then XTALO should be left unconnected.
I Power Down. PWRDWN is active LO. The assertion of this signal will initialize
the on-chip Control Registers to their default values, and will completely and
quietly power down the AD1843. If a crystal is not connected between XTALI
and XTALO, there must be a 24.576 MHz clock input on XTALI for at least
5 ms after this signal is asserted LO for proper operation. The AD1843 will not
be completely powered down until after this 5 ms period elapses. The AD1843
always finishes an in-progress power-up sequence before initiating a power-down
sequence, and vice versa. If the PWRDWN pin is asserted while a power-up sequence
is in progress, the 24.576 MHz clock signal on XTALI must persist for a worst
case maximum of 479 ms (power up = 470 ms, autocalibration = 4 ms, power
down = 5 ms) after PWRDWN is asserted. When INIT (Control Register
Address 0, Bit 15) is set to a “1,” the power-down sequence is complete. See
the “Power Management” section for important additional details.
I Reset. RESET is active LO. The assertion of this signal will initialize the on-chip
registers to their default values, and will completely power down the AD1843.
RESET is similar to PWRDWN, except that when PWRDWN is asserted, power
down is “quiet” and performed synchronously to the internal clocks. When RESET
is asserted, power down is “noisy” and performed asynchronously to the internal
clocks.
I Power-Down Mono Feedthrough. When the AD1843 mixer is powered down,
and PDMNFT is asserted HI, the Mono Input (MIN, PQFP Pin 19) is routed to
the Mono Output (MOUT, PQFP Pin 35), and the signal applied to MIN will
feedthrough to MOUT. When the AD1843 mixer is powered down and
PDMNFT is deasserted LO, the feedthrough of MIN to MOUT will be muted.
When the AD1843 mixer is not powered down, and MIN to MOUT feedthrough
is desired, the Mono Input Mix Mute (Control Register Address 8, Bit 15) and the
Mono Output Mute (Control Register Address 8, Bit 6) must be unmuted. During
power-down feedthrough, the signal applied to the MIN input appears only at
the MOUT output. During normal operation, the signal applied to the MIN
input appears at both the MOUT and the LOUT1 outputs. The state of the
PDMNFT pin should be changed when the AD1843 mixer is powered up. If the
state of PDMNFT is changed when the AD1843 is in total power-down, audible
pops and clicks will likely result.
O Common-Mode Voltage Output. Nominal 2.25 volt reference available externally
for dc-coupling and level-shifting. CMOUT should not be used where it will sink
or source current.
I Voltage Reference Filter. Voltage reference filter point for external bypassing only.
I Left Channel Filter. This pin requires a 1.0 µF capacitor to analog ground for
proper operation.
I Right Channel Filter. This pin requires a 1.0 µF capacitor to analog ground for
proper operation.
I Left Channel Antialias Filter. This pin requires a 1000 pF capacitor to analog
ground for proper operation.
I Right Channel Antialias Filter. This pin requires a 1000 pF capacitor to analog
ground for proper operation.
–10–
REV. 0
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