VSC7185TW Ver la hoja de datos (PDF) - Vitesse Semiconductor

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VSC7185TW

Quad Transceiver for Gigabit Ethernet and Fibre Channel

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Preliminary Data Sheet

VSC7185

On encountering a comma character, SYNi is driven HIGH. The SYNi pulse is asserted during both 5-bit

halves of the comma character. The SYNi signal is timed identically to data so that it can be captured by the

adjoining protocol logic along with RXi(0:4). Functional waveforms for synchronization are shown in Figure 2.

The first K28.5 shows the case where the comma is detected, but it is misaligned so a change in the output data

alignment is required. Note that one or two half-characters prior to the comma character may be corrupted by

the realignment process, but the comma character is always received and output correctly. The second K28.5

shows the case when a comma is detected and no phase adjustment is necessary. It illustrates the position of the

SYNi pulse in relation to the comma character on RXi(0:4).

When RSYN=0, there will always be a rising edge on RCi1 when the first five bits of the K28.5 character

are output. When RSYN=1, there will always be a rising edge on RCi1 between the first and second five bits of

the K28.5 character, and there may or may not be a falling edge on RCi1 coincident with the assertion of SYNi

(the first five bits of the K28.5 character). The behavior depends on the alignment of the new comma relative to

the current RCi(0:1) phase.

RSYN=0:

RCi0

Figure 2: Misaligned and Aligned K28.5 Characters

RCi1

RSYN=1:

RCi0

RCi1

Misaligned Comma: Stretched

Aligned Comma: In Phase

SYNi

RXi[0:4]

Corrupt

Corrupt

K28.5 (K28.5) A[0:4] A[5:9]

K28.5 (K28.5) B[0:4]

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52324-0, Rev. 3.0

8/28/00

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