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VSC7185

Quad Transceiver for Gigabit Ethernet and Fibre Channel

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7185

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Clock Recovery

The VSC7185 accepts differential high-speed serial input from the selected source (either the PECL SIi+/

SIi- pins or the internal SOi+/- data), extracts the clock and retimes the data. Equalizers are included in the

receiver to open the data eye and compensate for InterSymbol Interference (ISI) which may be present in the

incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by

an 8B/10B encoding scheme. For proper operation, the baud rate of the data stream to be recovered should be

within +200 ppm of ten (or twenty) times the RFC frequency. For example, Gigabit Ethernet systems would use

125MHz oscillators with a ±100ppm accuracy resulting in ±200 ppm between VSC7185 pairs.

Deserializer

The recovered serial bit stream is converted into a 5-bit parallel output character. The VSC7185 provides

complementary SSTL-2 recovered clocks, RCi0 and RCi1, which are at 1/10th of the serial baud rate. The

clocks are generated by dividing down the high-speed recovered clock which is phase-locked to the serial data.

The serial data is retimed, deserialized and output on RXi(0:4).

If serial input data is not present, or does not meet the required baud rate, the VSC7185 will continue to

produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency

under these circumstances will differ from its expected frequency by no more than +1%.

The receiver drives four sets of 5-pin RX data stable around the edges of RCi1 or RCi0. This is the case

when RSYN=0 (see Figure 2). When RSYN=1, the receive side timing and the transmit side timing are sym-

metrical in that the ASIC section receiving data from the RXi(0:4) buses may alternatively receive data from the

ASIC section driving the TXi(0:4) buses. In this mode, RXi(0:4) transition with the rising and falling edges of

RCi0 and RCi1.

Word Alignment

The VSC7185 provides 7-bit comma character recognition and data word alignment. Word synchronization

is enabled on all channels when SYNC=1. The serial data is converted back into the original 10-bit wide data

and recognizes the presence of the “Comma” pattern. This pattern is “0011111XXX”, where the leading zero

corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data

character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and

K28.7, which are defined for synchronization purposes. When SYNC=1 and an improperly aligned comma is

encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks

are aligned properly to RXi(0:4). This results in proper character and word alignment.

When the parallel data alignment changes in response to a improperly aligned comma pattern, data which

would have been presented on the parallel output port prior to the comma character may be lost. The comma

character itself and data subsequent to the comma character will always be output correctly and properly

aligned. When SYNC=0, the current alignment of the serial data is maintained indefinitely, regardless of data

pattern.

G52324-0, Rev. 3.0

8/28/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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