VSC7185TW Ver la hoja de datos (PDF) - Vitesse Semiconductor
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VSC7185TW Datasheet PDF : 18 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7185
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
Features
• Four Complete Transceiver Functions in a Single
Integrated Circuit
• SSTL-2 Compatible Parallel Data and Clocks
• 1.05Gb/s to 1.36Gb/s Operation per Channel
• Common Transmit Byte Clock
• TTL or PECL Reference Clock Input
• Per-Channel 1/10th Baud Rate Recovered Clocks
and Comma Detect Outputs
• Common Comma Detect Enable Input
• Common Serial / Parallel Loopback Controls
• Cable Equalization in Receivers
• JTAG Access Port
• 3.3V Power Supply, 2.5W Dissipation
• 208 pin, 23mm BGA Package
General Description
The VSC7185 is a full-speed quad Gigabit Ethernet and Fibre Channel Transceiver IC. 8B/10B encoded (or
equivalent scheme) transmit characters are serialized onto high-speed differential outputs (SOi+/-) at speeds up
to 1.36Gb/s. Each of the four transmitters has a 5-bit wide parallel input bus. Parallel data is latched in by an
internal clock running at up to 272MHz (2x the rate of the external common Transmit Byte Clock). Transmit
data must be presented synchronously with the common transmit byte clock. Each receiver samples the serial
receive data (SIi+/-), recovers the clock and data, deserializes it into 5-bit receive half-characters, outputs a
recovered 2x or 1x clock and detects “Comma” characters. The VSC7185 contains on-chip PLL circuitry for
synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams.
VSC7185 Block Diagram (1 of 4 Channels)
RXi(0:4)
5
QD
Serial to
Q Parallel D
QD
0
RCi1
RCi0
RSYN
SYNi
SYNC
PLUP
SLPN
TXi(0:4)
Comma
Detect
Loopback
Control
÷5 Clock
÷10
Recovery
Unit
5
DQ
Parallel
to Serial
1
0
DQ
1
TC
RFCT
RFC+
RFC-
RFCM
CAP0
CAP1
x10/x20
Clock
Multiply
Unit
SIi+
SIi-
SOi+
SOi-
RFCO
G52324-0, Rev. 3.0
8/28/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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