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109059790 Datasheet PDF : 50 Pages
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T8535B/T8536B Quad Programmable Codec
Preliminary Data Sheet
September 2001
Pin Information (continued)
Table 4. Pin Assignments, 68-Pin PLCC, Common Functions
Pin
1
2
3
4
5
10
11
12
13
14
24, 45,
58, 68
28, 40,
55, 66
56
57
59
60
65
67
Name
DO
DI
DCLK
CS
INTS
FILTV
PVCOIN
PVCO
PLLT
SGND
DGND
VDD
FS
BCLK
DX
DR
RST
NC
Type
O
I
I
I
I
PWR
—
—
—
GND
GND
PWR
Name/Description
Serial Data Output. This is a 3-state output.
Serial Data Input.
Serial Data Clock Input.
Chip Select Input. This lead determines the interval that the serial interface is
active.
Serial Interface Select. Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.
Frequency Synthesizer Power (5 V). This pin must be tied to VDD.
Internal Test Point. Do not connect to this lead.
Internal Test Point. Do not connect to this lead.
Synthesizer Test Point. Do not connect to this lead.
Synthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.
Digital Ground. Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is highly recommended.
Digital Power Supply (5 V).
I PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source
as BCLK.
I PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock
rates.
O PCM Transmit Data Output. This is a 3-state output.
I PCM Receive Data Input.
I Power-On Reset. A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1 µF capacitor for a power-on reset function, or it may be
driven by external logic. This lead has an internal pull-up.
— No Connect. This pin may be used as a tie point.
8
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