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109059824

Quad Programmable Codec

Agere -> LSI Corporation 

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Table of Contents (continued)

Figures

Page

Figure 1. Functional Block Diagram, Each Section...................................................................................................4

Figure 2. 44-Pin PLCC Pin Diagram .........................................................................................................................5

Figure 3. 68-Pin PLCC Pin Diagram .........................................................................................................................7

Figure 4. 100-Pin TQFP Pin Diagram .......................................................................................................................9

Figure 5. 64-Pin TQFP Pin Diagram .......................................................................................................................11

Figure 6. Command Frame Format, Master to Slave, Read or Write Commands ..................................................15

Figure 7. Command Frame Format, Slave to Master, Read Commands................................................................15

Figure 8. Write Operation, Normal Mode (Continuous DCLK) ................................................................................16

Figure 9. Write Operation, Normal Mode (Gapped DCLK) .....................................................................................16

Figure 10. Write Operation, Byte-by-Byte Mode (Gapped DCLK)...........................................................................17

Figure 11. Write Operation, Byte-by-Byte Mode (Continuous DCLK) .....................................................................17

Figure 12. Read Operation, Normal Mode (Continuous DCLK) ..............................................................................18

Figure 13. Read Operation, Normal Mode (Gapped DCLK) ...................................................................................19

Figure 14. Read Operation, Byte-by-Byte Mode (Gapped DCLK) ..........................................................................19

Figure 15. Read Operation, Byte-by-Byte Mode (Continuous DCLK) .....................................................................20

Figure 16. Fast Scan, Normal Mode (Continuous DCLK) .......................................................................................21

Figure 17. Fast Scan, Normal Mode (Gapped DCLK) ............................................................................................21

Figure 18. Fast Scan, Byte-by-Byte Mode (Gapped DCLK) ...................................................................................22

Figure 19. Fast Scan, Byte-by-Byte Mode (Continuous DCLK) ..............................................................................22

Figure 20. Hardware Reset Procedure ...................................................................................................................23

Figure 21. Internal Signal Processing .....................................................................................................................25

Figure 22. Serial Interface Timing, Normal Mode (One Byte Transfer and Continuous DCLK Shown) ..................35

Figure 23. Serial Interface Timing, Byte-by-Byte Mode (One Byte Transfer and Gapped DCLK Shown)...............35

Figure 24. Single-Clocking Mode (TXBITOFF = 0, RXBITOFF = 0, PCMCTRL2 = 0x00) ......................................37

Figure 25. Single-Clocking Mode (TXBITOFF = 1, RXBITOFF = 2, PCMCTRL2 = 0x01) ......................................37

Figure 26. Double-Clocking Mode (RXBITOFF = 0x20, PCMCTRL2 = 0x00) ........................................................39

Figure 27. POTS Interface ......................................................................................................................................44

Tables

Page

Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions............................................................................5

Table 2. Pin Assignments, 44-Pin PLCC, Common Functions .................................................................................6

Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions............................................................................7

Table 4. Pin Assignments, 68-Pin PLCC, Common Functions .................................................................................8

Table 5. Pin Assignments, 100-Pin TQFP, Per-Channel Functions..........................................................................9

Table 6. Pin Assignments, 100-Pin TQFP, Common Functions .............................................................................10

Table 7. Pin Assignments, 64-Pin TQFP, Per-Channel Functions..........................................................................11

Table 8. Pin Assignments, 64-Pin TQFP, Common Functions ...............................................................................12

Table 9. Bit Assignments for Fast Scan Mode ........................................................................................................20

Table 10. dc Characteristics....................................................................................................................................27

Table 11. Analog Interface ......................................................................................................................................28

Table 12. Power Dissipation ...................................................................................................................................28

Table 13. Gain and Dynamic Range .......................................................................................................................29

Table 14. Per-Channel Noise Characteristics .........................................................................................................31

Table 15. Distortion and Group Delay .....................................................................................................................32

Table 16. Crosstalk .................................................................................................................................................33

Table 17. Serial Control Port Timing .......................................................................................................................34

Table 18. PCM Interface Timing: Single-Clocking Mode ........................................................................................36

Table 19. PCM Interface Timing: Double-Clocking Mode .......................................................................................38

Table 20. Memory Mapping ....................................................................................................................................40

Table 21. Control Bit Definition ...............................................................................................................................41

Agere Systems Inc.

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