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109059790

Quad Programmable Codec

Agere -> LSI Corporation 

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Features

s 5 V operation

s Per-channel programmable gains, equalization,

termination impedance, and hybrid balance

s Programmable µ-law, linear, or A-law modes:

— Up to 256 time slots per frame

— Supports PCM data rates of 512 kbits/s to

16.384 Mbits/s

— Double-clock mode timing compatible with

ISDN standard interfaces

s Fully programmable time-slot assignment with bit

offset

s Analog and digital loopback test modes

s Serial microprocessor interface:

— Normal and byte-by-byte control modes

— Fast scan mode

s Six bidirectional control leads per channel, for

SLIC and line card function control

s Differential analog output:

— Mates directly to SLICs, eliminating external

components

s Sigma-delta converters with dither noise reduction

s Quad design to minimize package count on dense

line card applications

s Meets or exceeds ITU-T G.711—G.712 and rele-

vant Telcordia Technologies™ requirements

Description

The device consists of four independent channels of

codec and digital signal processing functions on one

chip. In addition to the classic A-to-D and D-to-A con-

version, each channel provides termination imped-

ance synthesis and a hybrid balance network.

The device is controlled by a serial microprocessor

interface, and a series of bidirectional I/O leads are

provided so that this control mechanism can be uti-

lized to operate the battery feed device, ringing volt-

age switches, etc. Common data and clock paths can

be shared over any number of devices. All the filter

coefficients, signal processing, SLIC, and test fea-

tures are accessible through this interface. This

serial interface can be operated at speeds up to

4.096 Mbits/s.

The choice of a PCM bus is also programmable, with

any channel capable of being assigned to any time

slot. The PCM bus can be operated at speeds up to

16.384 Mbits/s, allowing for a maximum of 256 time

slots. Separate transmit and receive interfaces are

available for 4-wire bus designs, or they can be

strapped together for a 2-wire PCM bus.

The device is available in four packages:

The T8536B 64-pin TQFP features five data latches

per channel and the 100-pin TQFP features six-data

latches per channel. Both devices have two PCM

ports and are pin-compatible with the T8538B 3.3 V

Quad Programmable Codec.

The T8536B 68-pin PLCC features six data latches

per channel and has one PCM port. This device is

pin-compatible with the T8534 Quad Programmable

Echo Canceller Codec.

The T8535B 44-pin PLCC has no data latches and

has one PCM port. This device is pin-compatible with

the T8533 Quad Programmable Echo Canceller

Codec.

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