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7507

Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance

Agere -> LSI Corporation 

Data Sheet

August 1999

T7507 Quad PCM Codec with Filters,

Termination Impedance, and Hybrid Balance

Functional Description (continued)

Microprocessor Serial Data Control and

L8567 SLIC/L7583 Switch (or EMR) Control

Interfaces (continued)

The serial data interface has pins for data in (DI), data

out (DO), chip select (CSEL), and control clock

(CCLK). Data is read by the microcontroller from the

output shift register at the T7507 DO lead. The T7507

reads data from the microcontroller into the data input

shift register at the DI lead. The loop status latch stores

updated supervision information from the SLIC and

switch until it is transferred to the DO shift register.

On the falling edge of CSEL, the first bit of DO output

data becomes valid and ready for transmission in the

time specified by tCSLCCL. On the next falling CCLK

edge, the microprocessor will read the first bit of valid

data from the T7507 DO output. Also, on this first falling

CCLK edge, the T7507 will read the first bit of control

information on the DI input from the microcontroller.

Thus, upon the falling CSEL edge, the microcontroller

must have valid data ready at its data out lead in a time

specified by tCIVCCL.

On the next seven falling CCLK edges, the remaining

seven status bits are read by the microcontroller at the

T7507 DO lead and the remaining 7 control input bits

are read by the T7507 at the DI lead from the micro-

controller.

During the time tCCLCSH, which is the period after the

eight falling CCLK edges, the data at the DI register is

applied to the T7507 codec and made available to the

L8567 SLIC and L7583 switch input data latches. Data

is applied only if CSEL is low and has remained low on

the eighth negative edge of CCLK.

Upon the falling edge of CSEL, DO data is passed from

the loop status latch to the DO shift register. During the

period when CSEL is low, DO status data will not be

passed from the loop status latch to the DO shift regis-

ter. Consecutive read/write periods are not allowed.

CSEL must remain high for a specified time, tCSHCSL,

before CSEL can transition low again.

During CSEL low interval, the T7507 generates an EN

pulse low for one of the four channels served by the

particular T7507. These EN pulses are generated

sequentially. Thus, if EN0 is generated on a given

CSEL low, EN1 will be generated during the next CSEL

low, etc. Only one of the four EN outputs associated

with a given T7507 codec will be low during a given

CSEL interval.

Enable Transfers when CCLK Is Bursted with

CSEL

When EN is low, status information from the SLIC and

switch is updated in the T7507 8-bit loop status latch.

This data will be transferred into the data out shift regis-

ter and shifted out to the microcontroller on the next

CSEL cycle. Thus, to make a write from the L8567

SLIC or L7583 switch, it takes two CSEL cycles: the

first to create an EN pulse for a given channel and to

shift updated status information to the 8-bit status latch,

and the second CSEL cycle to shift the updated chan-

nel information to the microcontroller. Each time the

CSEL goes low and status information is shifted to the

microcontroller, only one of the four channels has new

status data; the other channels are shifting out status

data that has previously been presented to the micro-

controller. Thus, it takes five CSEL cycles to a T7507

device to ensure that supervision data for each of the

four channels associated with the T7507 device has

been updated.

When EN goes low, updated control information is also

fed to the SLIC and switch from the T7507. Since EN

for each channel is generated sequentially during suc-

cessive CSEL, four CSELs to a given T7507 device are

required to ensure that updated control information is

given to each of the four channels.

Note that to apply ringing, before the ring relay is acti-

vated to apply power ringing to the subscriber loop, the

L8567 SLIC must first be changed from the low-power

scan mode to the active mode. This is because the ring

trip detector is not active when the L8567 SLIC is in the

low-power scan mode. Thus, application of ringing to a

given channel may require as many as eight CSEL

cycles to the T7507 associated with the channel.

Enable Transfers when CCLK Is Not

Restricted to CSEL Low

The T7507 will continue to generate EN pulses

sequentially, free-running with CCLK falling edges,

when CSEL is not applied low. Thus, if there are long

periods of time when CSEL low is not presented to a

given T7507 device, enable pulse low will be generated

sequentially during this time. This feature allows for the

most recent SLIC and switch status information to be

maintained in the 8-bit loop status latch during long

periods of time when CSEL to a given T7507 device is

maintained high.

Lucent Technologies Inc.

9

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