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7507

Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance

Agere -> LSI Corporation 

T7507 Quad PCM Codec with Filters,

Termination Impedance, and Hybrid Balance

Data Sheet

August 1999

Functional Description (continued)

Enable Transfers when CCLK Is Not

Restricted to CSEL Low (continued)

If CSEL drops low, during the time an EN for a given

channel is low, the write cycle to/from the codec will be

aborted. However, the EN pulse that will be generated

during the eight CCLK cycles that CSEL is low will be

for the channel whose EN pulse was aborted by the

CSEL dropping low. Thus, for example, if EN2 is low

and during the time EN2 is low CSEL is also low, EN2

will immediately go high and any associated write is

aborted. Then the EN that is generated because CSEL

is low is for channel 2.

The T7507 generates the required enable control sig-

nals for the L8567 input data latches, the output data

latches, and the L7583 input data latch. A logic low on

the L8567 or L7583 latch enable input allows data to

flow through the latch. A logic high on the latch enable

of the L8567 or L7583 latches the latch. The latch

enable is output on a per-line basis from the EN0c,

EN1c, EN2c, and EN3c outputs of the T7507. The

L8567 SLIC and L7583 latches are level sensitive, so

when ENx is low, the data from the SLIC and switch

latch flows directly to the T7507 loop status latch. After

a high-to-low CSEL transition, on the next falling edge

of CCLK, data is transferred from the loop status latch

to the serial shift register. Therefore, it is not desirable

to update the loop status register on this CCLK edge.

For this reason, EN pulses are generated during the

rising edge of CCLK.

Note that loop status information from the four chan-

nels is accepted on a multiplexed basis at the NSTATc

input of the T7507. This information is decoded by the

T7507 and placed at the appropriate bit in the 8-bit out-

put word. NSTAT is a wired-OR of the loop closure and

ring trip status from the L8567 SLIC.

Thermal shutdown information from the four SLICs is

accepted on a multiplexed basis at the NTSDc input of

the T7507. Thermal shutdown information from the

L7583 switch is accepted on a per-line basis from the

four L7583s associated with the quad T7507. The ther-

mal shutdown information from the SLICs is decoded

by the T7507 and then ANDed with the thermal shut-

down information from the corresponding L7583. This

thermal shutdown information for the SLIC and switch

is then placed at the appropriate bit in the 8-bit output

word.

The control word contains control information for the

T7507, L8567 SLIC, and L7583 switch. Thus, the con-

trol bits for the L8567 SLIC and L7583 switch need to

be transferred via the latched parallel control interface.

SLIC control information for the four channels is trans-

10

ferred on a multiplexed basis through the B0c and B1c

output leads on the T7507. L7583 control information

(or L8567 relay driver information) is transferred on a

multiplexed basis through the RD1c, RD2c, and RD3c

output leads.

Three features for the T7507 can be programmed via

the serial data interface. The channel receive gain and

codec powerup or powerdown are set on a per-channel

basis. Delayed and nondelayed timing mode is set glo-

bally; all four channels are set to the same mode via

the serial data bus. Additionally, PCM time-slot assign-

ment is set via the serial data input bus.

The L8567 B0, B1 state control inputs are latched data

inputs. Control data is sent to these inputs via the B0c

and B1c outputs of the T7507. The B0c and B1c out-

puts of the T7507 are meant to control the four SLICs

associated with the quad T7507.

Switch control information is sent to the INRING,

INTESTin, or INTESTin logic control inputs of the L7583

switch, or to the RD1I, RD2I, and RD3I relay driver con-

trol inputs of the L8567 SLIC (if EMRS are used) via

the RD1c, RD2c, and RD3c T7507 parallel data control

outputs. Again, the L7583 state control inputs and the

L8567 relay driver control inputs are latched, so control

information from the RD1c, RD2c, and RD3c T7507

control outputs are meant to control four lines.

The L8567 SLIC outputs loop status information via the

latched NSTAT output. NSTAT is a wired-OR or the out-

puts of the L8567 SLIC’s loop closure detector and ring

trip detector. The loop status information is input to the

T7507 via the NSTATc input. Since the L8567 SLIC

NSTAT bit is latched, the SLIC output from the four

channels associated with the T7507 are accepted at

NSTATc.

The L8567 SLIC also outputs a thermal shutdown flag

via the latched NTSD output. This thermal shutdown

information is input to the T7507 via the NTSDc input.

Since the L8567 SLIC NSTAT and NTSD bits are

latched, the SLIC output from the four channels associ-

ated with the T7507 are accepted at NSTATc and

NTSD, respectively.

The L7583 also outputs thermal shutdown status via

the TSD output. The TSD output on the L7583 is not

latched, so the TSD information is input to the T7507

for the four channels associated with the quad T7507

on a per-line basis via the NTSD0, NTSD1, NTSD2,

and NTSD3 T7507 inputs.

The multiplexed thermal shutdown information from the

four L8567 SLICs and the per-line thermal shutdown

information from the four L7583 switches are manipu-

lated by the T7507 into a per-channel thermal shut-

down bit and output on the serial data output DO pin.

Lucent Technologies Inc.

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