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LU5X34F

Quad Gigabit Ethernet Transceiver

Agere -> LSI Corporation 

Preliminary Data Sheet

July 2000

LU5X34F

Quad Gigabit Ethernet Transceiver

Overview

The LU5X34F is a low-cost, low-power quad trans-

ceiver. It is used for data transmission over fiber or

coaxial media in conformance with IEEE * 802.3z

Gigabit Ethernet specification and Fibre Channel

ANSI † X3T11 at 1.0 Gbits/s and

1.25 Gbits/s.

Each of the four transceivers independently provides

complete serialize/deserialize (SERDES) and trans-

mit and receive functions. The device is available in a

217-pin PBGA package.

The transmitter section accepts TTL compatible data

at the 10-bit parallel input port. The parallel input

data is latched on the rising edge of TXCLKx. It also

accepts the low-speed, TTL compatible system

clock, REFCLK, and uses this clock to synthesize the

internal high-speed serial bit clock. The serialized

data is then available at the differential PECL out-

puts, terminated in 50 Ω or 75 Ω to drive either an

optical transmitter or coaxial media.

The receive section receives high-speed serial data

at its differential PECL input port. This data is fed to

the digital clock recovery section, which generates a

recovered clock and retimes the data. The retimed

data is deserialized and presented as 10-bit parallel

data on the output port. A divided-down version of

the recovered clock, synchronous with parallel data

bytes, is also available as a TTL compatible output.

The receive section recognizes the comma character

and aligns the comma-containing byte on the word

boundary, when ENCDET = 1.

s 100 MHz—125 MHz differential or single-ended

reference clock.

s 10-bit parallel, TTL-compatible I/O interface.

s 8-bit/10-bit encoded data.

s High-speed comma character recognition (K28.1,

K28.5, K28.7) for latency-sensitive applications

and alignment to word boundary.

s Two 50 MHz—62.5 MHz receive-byte clocks.

s Single analog PLL design requires no external

components for the frequency synthesizer.

s Novel digital data lock in receiver avoids the need

for multiple analog PLLs.

s Expandable beyond four serializer/deserializers.

s PECL high-speed interface I/O for use with optical

transceiver or coaxial copper media.

s Requires one external resistor for PECL output ref-

erence-level definition.

s Low-power digital CMOS technology.

s Less than 2 W total power dissipation per quad

transceiver.

s 3.3 V ± 5% power supply.

s 0 °C—70 °C ambient temperature.

s Stand-alone transceiver product.

s Transceiver macrocell template.

s Available in 217-pin PBGA package.

Features

s Designed to operate in Ethernet, fibre channel,

Firewire ‡, or backplane applications.

s Operationally compliant to IEEE 802.3z Gigabit

Ethernet specification.

s Operationally compliant to Fibre Channel ANSI

X3T11. Provides FC-0 services at 1.0 Gbits/s—

1.25 Gbits/s (10-bit encoded data rate).

* IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

† ANSI is a registered trademark of American National Standards

Institute.

‡ FireWire is a registered trademark of Apple Computer, Inc.

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