MM74C175M Ver la hoja de datos (PDF) - Fairchild Semiconductor
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MM74C175M Datasheet PDF : 6 Pages
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October 1987
Revised January 1999
MM74C175
Quad D-Type Flip-Flop
General Description
The MM74C175 consists of four positive-edge triggered D-
type flip-flops implemented with monolithic CMOS technol-
ogy. Both are true and complemented outputs from each
flip-flop are externally available. All four flip-flops are con-
trolled by a common clock and a common clear. Informa-
tion at the D-type inputs meeting the set-up time
requirements is transferred to the Q outputs on the posi-
tive-going edge of the clock pulse. The clearing operation,
enabled by a negative pulse at Clear input, clears all four Q
outputs to logical “0” and Q's to logical “1”.
All inputs are protected from static discharge by diode
clamps to VCC and GND.
Features
s Wide supply voltage range: 3V to 15V
s Guaranteed noise margin: 1.0V
s High noise immunity: 0.45 VCC (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
Ordering Code:
Order Number Package Number
Package Description
MM74C175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74C175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Truth Table
Each Flip-Flop
Inputs
Clear Clock
D
L
X
X
H
↑
H
H
↑
L
H
H
X
H
L
X
H = HIGH Level
L = LOW Level
X = Irrelevant
↑ = Transition from LOW-to-HIGH level
NC = No Change
Outputs
Q
Q
L
H
H
L
L
H
NC
NC
NC
NC
© 1999 Fairchild Semiconductor Corporation DS005900.prf
www.fairchildsemi.com
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