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MC14526BFL1

Presettable 4-Bit Down Counters

ON Semiconductor 

MC14526B

APPLICATIONS INFORMATION

Divide–By–N, Single Stage

Figure 11 shows a single stage divide–by–N application.

To initialize counting a number, N is set on the parallel

inputs (P0, P1, P2, and P3) and reset is taken high

asynchronously. A zero is forced into the master and slave

of each bit and, at the same time, the “0” output goes high.

Because Preset Enable is tied to the “0” output, preset is

enabled. Reset must be released while the Clock is high so

the slaves of each bit may receive N before the Clock goes

low. When the Clock goes low and Reset is low, the “0”

output goes low (if P0 through P3 are unequal to zero).

The counter downcounts with each rising edge of the

Clock. When the counter reaches the zero state, an output

pulse occurs on “0” which presets N. The propagation delays

from the Clock’s rising and falling edges to the “0” output’s

rising and falling edges are about equal, making the “0”

output pulse approximately equal to that of the Clock pulse.

The Inhibit pin may be used to stop pulse counting. When

this pin is taken high, decrementing is inhibited.

Cascaded, Presettable Divide–By–N

Figure 12 shows a three stage cascade application. Taking

Reset high loads N. Only the first stage’s Reset pin (least

significant counter) must be taken high to cause the preset

for all stages, but all pins could be tied together, as shown.

When the first stage’s Reset pin goes high, the “0” output

is latched in a high state. Reset must be released while Clock

is high and time allowed for Preset Enable to load N into all

stages before Clock goes low.

When Preset Enable is high and Clock is low, time must

be allowed for the zero digits to propagate a Cascade

Feedback to the first non–zero stage. Worst case is from the

most significant bit (M.S.B.) to the L.S.B., when the L.S.B.

is equal to one (i.e. N = 1).

After N is loaded, each stage counts down to zero with

each rising edge of Clock. When any stage reaches zero and

the leading stages (more significant bits) are zero, the “0”

output goes high and feeds back to the preceding stage.

When all stages are zero, the Preset Enable automatically

loads N while the Clock is high and the cycle is renewed.

N

VDD

VSS

fin

P0

Q0

P1

Q1

P2

Q2

P3

Q3

CF

RESET

“0”

INHIBIT

CLOCK

PE

BUFFER

fin

N

LSB

N0 N1 N2 N3

fin

VSS

VDD

P0 P1 P2 P3 Q0 Q1 Q2 Q3

CLOCK

INHIBIT

RESET “0”

CF

PE

LOAD

N

10 KΩ

VSS

Figure 11. ÷ N Counter

N4 N5 N6 N7

P0 P1 P2 P3 Q0 Q1 Q2 Q3

CLOCK

CF

INHIBIT

VSS

RESET “0” PE

MSB

N8 N9 N10 N11

P0 P1 P2 P3 Q0 Q1 Q2 Q3 VDD

CLOCK

CF

INHIBIT

VSS

RESET “0” PE

Figure 12. 3 Stages Cascaded

BUFFER

fin

N

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