ICL7109 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

ICL7109

12-Bit, Microprocessor Compatible A/D Converter

Intersil 

ICL7109

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

fOSC = 0.45/RC

COSC > 50pF; ROSC > 50kΩ

fOSC (Typ) = 60kHz

or

fOSC (Typ) = 3.58MHz Crystal

• OSCILLATOR PERIOD

tOSC = RC/0.45

tOSC = 1/3.58MHz (Crystal)

• INTEGRATION CLOCK FREQUENCY

fCLOCK = fOSC (RC Mode)

fCLOCK = fOSC/58 (Crystal)

tCLOCK = 1/fCLOCK

• INTEGRATION PERIOD

tINT = 2048 x tCLOCK

• 60/50Hz REJECTION CRITERION

tINT/t60Hz or tlNT/t50Hz = Integer

• OPTIMUM INTEGRATION CURRENT

IINT = 20µA

• FULL-SCALE ANALOG INPUT VOLTAGE

VlNFS Typically = 200mV or 2V

• INTEGRATE RESISTOR

RINT = V----I-I-I-N-N---F-T---S-

• INTEGRATE CAPACITOR

CINT = (---t--I--N---V-T---I-)-N-(---IT--I-N-----T---)

• INTEGRATOR OUTPUT VOLTAGE SWING

VINT = (---t--I--N---C-T----)I-N-(---IT--I-N-----T---)

• VINT MAXIMUM SWING

(V- + 0.5V) < VINT < (V+ - 0.5V)

VINT (Typ) = 2V

• DISPLAY COUNT

COUNT = 2048 × V----V-R---I-E-N----F--

• CONVERSION CYCLE

tCYC = tCL0CK x 8192

(In Free Run Mode, Run/HOLD = 1)

when fCLOCK = 60kHz, tCYC = 133ms

• COMMON MODE INPUT VOLTAGE

(V- + 2.0V) < VlN < (V+ - 2V)

• AUTO-ZERO CAPACITOR

0.01µF < CAZ < 1µF

• REFERENCE CAPACITOR

0.1µF < CREF < 1µF

• VREF

Biased between V+ and V-

VREF ≅ V+ - 2.8V

Regulation lost when V+ to V- ≤ 6.4V.

If VREF is not used, float output pin.

• POWER SUPPLY: DUAL ±5.0V

V+ = +5V to GND

V- = -5V to GND

• OUTPUT TYPE

Binary Amplitude with Polarity and Overrange Bits

Tips: Always tie TEST pin HIGH.

Don’t leave any inputs floating.

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