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Número de pieza
componentes Descripción
CXG1030N Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXG1030N
Power Amplifier for PHS
Sony Semiconductor
CXG1030N Datasheet PDF : 5 Pages
1
2
3
4
5
Block Diagram
V
DD
1 V
DD
2 V
DD
3
RF
IN
RF
OUT
V
GG
1
V
CTL
V
GG
2
Gate Bias Circuit
Pin Configuration
1
GND
RF
IN
GND
V
DD
1
GND
V
DD
2
GND
V
DD
3
Gate adjustment pin
1k
Ω
V
GG
2
V
GG
1
CXG1030N
16
GND
V
GG
1
V
CTL
GND
V
GG
2
GND
RF
OUT
GND
Recommended Current Adjustment Method
(1) V
GG
2/P
IN
separate adjustment
(V
GG
2 adjustment 1)
(P
IN
adjustment 1)
When the RF input
(P
IN
) is off, the current
consumption (I
DD
) is
adjusted to 170 mA.
The output power
(P
OUT
) is adjusted
to 21.0 dBm.
Variation of I
DD
and
P
OUT
due to adjustment
I
DD
=170±20 mA
P
OUT
=21.0 dBm
(V
GG
2 adjustment 2)
The current
consumption (I
DD
)
is finely adjusted to
170 mA.
I
DD
=170 mA
P
OUT
=21.0±0.2 dBm
(P
IN
adjustment 2)
The output power
(P
OUT
) is finely
adjusted to 21.0 dBm.
I
DD
=170±5 mA
P
OUT
=21.0 dBm
(2) Simple adjustment
(I
DD
read)
When the RF input (P
IN
)
is off, the gate voltage
(V
GG
2) is set to 0.4 V
and I
DD
is read.
Variation of I
DD
and P
OUT
due to adjustment
(V
GG
2 setting)
The formula
∗
1
where
V
GG
2=f (I
DD
: V
GG
2=0.4 V)
is used to set V
GG
2.
∗
1
e.g. V
GG
2=a-b
×
I
DD
(P
IN
adjustment)
The output power (P
OUT
)
is adjusted to 21.0 dBm.
I
DD
=170±5 mA
P
OUT
=21.0 dBm
—2—
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