STV7697A Ver la hoja de datos (PDF) - STMicroelectronics
Número de pieza
componentes Descripción
Fabricante
STV7697A Datasheet PDF : 16 Pages
| |||
BLOCK DIAGRAM
CLK 93
SIN (SOUT) 89
STB 92
VCC
BLK 86
VCC
POL 85
64-BIT SHIFT REGISTER
P1
P64
S1
Q1Q2
LATCH
S64
Q63Q64
STV7697A VSSP
VPP
80
OUT1
VSSP
VPP
1
OUT64
STV7697A
VCC
87 F/R
91 SOUT (SIN)
VSSSUB
Pins 38-43
VSSLOG
Pins 39-40-42-94
VCC
Pins 41-90
VSSP
Pins 34-35-36-45-46
47-82-83-98-99
VPP
Pins 33-37-44-48
81-84-97-100
CIRCUIT DESCRIPTION
The STV7697A contains all the logic and the pow-
er circuits necessary to drive rows of a Plasma
Display Panel (P. D. P.). The state of the displayed
line is loaded into the shift register. Data are shift-
ed at each low to high transition of the (CLK) shift
clock. After 64 shifts the first bit is available at the
serial output. This output can be used to cascade
several drivers to perform any vertical resolution.
The forward / reverse (F/R) input is used to select
the direction of the shift register, data input/output
status is set according to the selected direction.
SIN, CLK, STB inputs
are Smith trigger inputs . If not used on the appli-
cation, F/R, BLK, POL logical inputs are internaly
pulled to level ”1”. The maximum frequency of the
shift clock is 20 MHz.
All the data are memorized into the latch stage
when the strobe input (STB) is pulled high.
Blanking input (BLK) forces the power outputs to
high level when pulled high with polarity input
(POL) at high level and forced to low level with
POL at low level.
The level of the power output is inverted when the
polarity command (POL) is pulled high.
Sustain current must not be sunk in the power out-
put to VPP when the power supply is applied.
VSSLOG and VSSSUB must be connected as close
as possible to the logical reference ground of the
application.
Shift Register Truth Table
In put
Input /Outp ut
Shift Register
Fun ction
F/R CLK SIN SOUT Output Q
H Rise IN OUT Forward Shift
H H or L IN OUT Steady
L Rise OUT IN Reverse Shift
L H or L OUT IN Steady
7/15
3
Share Link: 