MT90500AL Ver la hoja de datos (PDF) - Mitel Networks

Número de pieza

componentes Descripción

Fabricante

MT90500AL

Multi-Channel ATM AAL1 SAR

Mitel Networks 

MT90500

Table 49 -

Table 50 -

Table 51 -

Table 52 -

Table 53 -

Table 54 -

Table 55 -

Table 56 -

Table 57 -

Table 58 -

Table 59 -

Table 60 -

Table 61 -

Table 62 -

Table 63 -

Table 64 -

Table 65 -

Table 66 -

Table 67 -

Table 68 -

Table 69 -

Table 70 -

Table 71 -

Table 72 -

Table 73 -

Table 74 -

Table 75 -

Table 76 -

Table 77 -

Table 78 -

Table 79 -

Table 80 -

Table 81 -

Table 82 -

Table 83 -

Table 84 -

Table 85 -

Table 86 -

Table 87 -

Table 88 -

Table 89 -

Table 90 -

Table 91 -

Table 92 -

Table 93 -

Table 94 -

Table 95 -

Table 96 -

Table 97 -

Table 98 -

TDM I/O Register ........................................................................................................................... 100

TDM Bus Type Register................................................................................................................. 101

Local Bus Type Register ................................................................................................................ 102

TDM Bus to Local Bus Transfer Register....................................................................................... 102

Local Bus to TDM Bus Transfer Register....................................................................................... 103

TX Circular Buffer Control Structure Base Register....................................................................... 103

External to Internal Memory Control Structure Base Register ....................................................... 103

TX Circular Buffer Base Address Register..................................................................................... 104

TDM Read Underrun Address Register ......................................................................................... 104

TDM Read Underrun Count Register............................................................................................. 104

Clock Module General Control Register......................................................................................... 104

Clock Module General Status Register .......................................................................................... 105

Master Clock Generation Control Register .................................................................................... 106

Master Clock / CLKx2 Division Factor............................................................................................ 107

Timing Reference Processing Control Register ............................................................................. 107

Event Count Register ..................................................................................................................... 108

CLKx1 Count - Low Register.......................................................................................................... 108

CLKx1 Count - High Register......................................................................................................... 108

DIVX Register ................................................................................................................................ 109

DIVX Ratio Register ....................................................................................................................... 109

SRTS Transmit Gapping Divider Register ..................................................................................... 109

SRTS Transmit Byte Counter Register .......................................................................................... 110

SRTS Receive Gapping Divider Register ...................................................................................... 110

SRTS Receive Byte Counter Register ........................................................................................... 110

Output Enable Registers ................................................................................................................ 111

Absolute Maximum Ratings ........................................................................................................... 112

Recommended Operating Conditions ............................................................................................ 112

DC Characteristics ......................................................................................................................... 112

Main TDM Bus Output Clock Parameters ...................................................................................... 114

Main TDM Bus Data Output Parameters ....................................................................................... 116

Main TDM Bus Input Clock Parameters......................................................................................... 117

Main TDM Bus Input Data Parameters .......................................................................................... 117

Local TDM Bus Clock Parameters ................................................................................................. 120

Local TDM Bus Data Output Parameters....................................................................................... 120

Local TDM Bus Data Input Parameters ......................................................................................... 122

Intel Microprocessor Interface Timing - Read Cycle Parameters................................................... 124

Intel Microprocessor Interface Timing - Write Cycle Parameters................................................... 125

Motorola Microprocessor Interface Timing - Read Cycle Parameters ........................................... 126

Motorola Microprocessor Interface Timing - Write Cycle Parameters............................................ 127

MCLK - Master Clock Input Parameters ........................................................................................ 128

External Memory Interface Timing - Clock Parameters ................................................................. 128

External Memory Interface Timing - Read Cycle Parameters........................................................ 128

External Memory Interface Timing - Write Cycle Parameters ........................................................ 128

Primary UTOPIA Interface Parameters - Transmit......................................................................... 131

Primary UTOPIA Interface Parameters - Receive.......................................................................... 132

Secondary UTOPIA Parameters Timing ........................................................................................ 133

SRTS Interface Parameters ........................................................................................................... 134

Message Channel Parameters....................................................................................................... 134

Boundary-Scan Test Access Port Timing ...................................................................................... 136

MT90500 Connections to 18-bit Synchronous SRAM.................................................................... 138

9

Share Link: