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MT90500AL

Multi-Channel ATM AAL1 SAR

Mitel Networks 

MT90500

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Primary UTOPIA Bus Pins ................................................................................................................19

Secondary UTOPIA Bus Pins ...........................................................................................................20

Microprocessor Bus Interface Pins ...................................................................................................20

External Memory Interface Pins ........................................................................................................21

Master Clock, Test, and Power Pins .................................................................................................22

TDM Port Pins...................................................................................................................................23

Reset State of I/O and Output Pins...................................................................................................24

Pinout Summary................................................................................................................................25

Memory Size Combinations ..............................................................................................................39

Effect of PSEL Field on P-byte Generation.......................................................................................53

Register Summary ............................................................................................................................82

Main Control Register .......................................................................................................................84

Main Status Register.........................................................................................................................84

Window to External Memory Register - CPU ....................................................................................85

Read Parity Register .........................................................................................................................85

Memory Configuration Register ........................................................................................................86

TX_SAR Control Register .................................................................................................................87

TX_SAR Status Register...................................................................................................................87

TX_SAR Scheduler Base Register ...................................................................................................88

TX_SAR Frame End Register ...........................................................................................................88

TX_SAR End Ratio Register .............................................................................................................88

TX_SAR Control Structure Base Address Register ..........................................................................89

Transmit Data Cell FIFO Base Address Register .............................................................................89

Transmit Data Cell FIFO Write Pointer Register ...............................................................................89

Transmit Data Cell FIFO Read Pointer Register...............................................................................90

RX_SAR Control Register.................................................................................................................91

RX_SAR Status Register ..................................................................................................................92

RX_SAR Misc. Event ID Register .....................................................................................................92

RX_SAR Misc. Event Counter Register ............................................................................................92

RX_SAR Underrun Event ID Register...............................................................................................93

RX_SAR Underrun Event Counter Register .....................................................................................93

RX_SAR Overrun Event ID Register.................................................................................................93

RX_SAR Overrun Event Counter Register .......................................................................................93

UTOPIA Control Register..................................................................................................................94

UTOPIA Status Register ...................................................................................................................94

VPI / VCI Concatenation Register.....................................................................................................95

VPI Match Register ...........................................................................................................................95

VPI Mask Register ............................................................................................................................95

VCI Match Register ...........................................................................................................................95

VCI Mask Register ............................................................................................................................96

VPI Timing Register ..........................................................................................................................96

VCI Timing Register ..........................................................................................................................96

Lookup Table Base Address Register...............................................................................................96

Receive Data Cell FIFO Base Address Register ..............................................................................97

Receive Data Cell FIFO Write Pointer Register ................................................................................97

Receive Data Cell FIFO Read Pointer Register................................................................................97

TDM Interface Control Register ........................................................................................................98

TDM Interface Status Register..........................................................................................................99

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