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TC835CBU

PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER

TelCom Semiconductor Inc => Microchip 

PERSONAL COMPUTER

DATA ACQUISITION A/D CONVERTER

TC835

The new measurement cycle begins with a 10,001-

count auto-zero phase. At the end of this phase the busy

signal goes high.

STROBE Output (Pin 26)

During the measurement cycle, the STROBE control

line is pulsed low five times. The five low pulses occur in the

center of the digit drive signals (D1, D2, D3, D5, Figure 8).

D5 (MSD) goes high for 201 counts when the measure-

ment cycles end. In the center of the D5 pulse, 101 clock

pulses after the end of the measurement cycle, the first

STROBE occurs for one-half clock pulse. After the D5 digit

strobe, D4 goes high for 200 clock pulses. The STROBE

goes low 100 clock pulses after D4 goes high. This continues

through the D1 digit drive pulse.

The digit drive signals will continue to permit display

scanning. STROBE pulses are not repeated until a new

measurement is completed. The digit drive signals will not

continue if the previous signal resulted in an overrange

condition.

The active low STROBE pulses aid BCD data transfer to

UARTs, processors and external latches. (See Application

Note 16.)

BUSY Output (Pin 21)

At the beginning of the signal-integration phase, BUSY

goes high and remains high until the first clock pulse after the

integrator zero crossing. BUSY returns to the logic "0" state

after the measurement cycle ends in an overrange condi-

tion. The internal display latches are loaded during the first

clock pulse after BUSY, and are latched at the clock pulse

end. The BUSY signal does not go high at the beginning of

the measurement cycle, which starts with the auto-zero

cycle.

OVERRANGE Output (Pin 27)

If the input signal causes the reference voltage integra-

tion time to exceed 20,000 clock pulses, the OVERRANGE

output is set to a logic "1." The overrange output register is

set when BUSY goes low, and is reset at the beginning of the

next reference-integration phase.

UNDERRANGE Output (Pin 28)

If the output count is 9% of full scale or less (≤1800

counts), the underrange register bit is set at the end of

BUSY. The bit is set low at the next signal-integration phase.

POLARITY Output (Pin 23)

A positive input is registered by a logic "1" polarity signal.

The polarity bit is valid at the beginning of reference inte-

grate and remains valid until determined during the next

conversion.

TC835

OUTPUTS

BUSY

END OF CONVERSION

*

B1–B8

D5 (MSD)

DATA

D4

DATA

D3

DATA

STROBE

200

COUNTS

D2 D1 (LSD) D5

DATA DATA DATA

NOTE ABSENCE

OF STROBE

D5

201

COUNTS

200

COUNTS

D4

200

COUNTS

D3

200

COUNTS

D2

200

COUNTS

D1

200

COUNTS

*DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE

PULSE IS DEPENDENT ON ANALOG INPUT.

Figure 8. Strobe Signal Pulses Low Five Times per Conversion

The polarity bit is valid even for a zero reading. Signals

less than the converter's LSB will have the signal polarity

determined correctly. This is useful in null applications.

DIGIT Drive Outputs (Pins 12, 17, 18, 19 and 20)

Digit drive signals are positive-going signals. The scan

sequence is D5 to D1. All positive pulses are 200 clock pulses

wide, except D5, which is 201 clock pulses wide.

All five digits are scanned continuously, unless an

overrange condition occurs. In an overrange condition, all

digit drives are held low from the final STROBE pulse until

the beginning of the next reference-integrate phase. The

scanning sequence is then repeated. This provides a blink-

ing visual display indication.

BCD Data Outputs (Pins 13, 14, 15 and 16)

The binary coded decimal (BCD) bits B8, B4, B2, B1, are

positive-true logic signals. The data bits become active

simultaneously with the digit drive signals. In an overrange

condition, all data bits are at a logic "0" state.

3-72

TELCOM SEMICONDUCTOR, INC.

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