ICS507-01 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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ICS507-01 Datasheet PDF : 5 Pages
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ICS507-01/02
PECL Clock Synthesizer
Applications
High Frequency Differential PECL Oscillators: The ICS507 plus a low frequency, fundamental mode
crystal can build a high frequency differential output oscillator. For example, a 10 MHz crystal connected
to the ICS507 with the 12X output selected (S1=0, S0=1) produces a 120 MHz PECL output clock.
High Frequency TCXO: Extending the previous application, an inexpensive, low frequency TCXO can be
built and the output frequency can be multiplied using the ICS507. Since the output of the chip is phase-
locked to the input, the ICS507 has no temperature dependence, and the temperature coefficient of the
combined system is the same as that of the low frequency TCXO.
High Frequency VCXO: The bandwidth of the PLL is guaranteed to be greater than 10 kHz. This means
that the PLL will track any modulation on the input with a frequency of less than 10 kHz. By using this
property, a low frequency VCXO can be built, and the output can then be multiplied with the ICS507 to
give a high frequency output, thereby producing a high frequency VCXO.
Decoupling and External Components
The ICS507 requires a 0.01µF decoupling capacitor to be connected between VDD and GND on pins 2
and 5. It must be connected close to the ICS507. Other VDD and GND connections should be
connected to those pins, or to the VDD and GND planes on the board. A resistor must be connected
between the RES (pin 10) and VDD. Another four resistors are needed for the PECL outputs as shown on
the block diagram on page 1. Suggested values of these resistors are shown in the Block Diagram, but they
can be varied to change the differential pair output swing, and the DC level; refer to MAN09.
MDS 507 C
4
Revision 042600
Printed 11/13/00
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