AD678 Ver la hoja de datos (PDF) - Analog Devices
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AD678 Datasheet PDF : 14 Pages
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AD678
Symbol
28-Lead DIP 44-Lead
Pin No.
JLCC Pin No. Type
PIN DESCRIPTION
Name and Function
AGND
7
AIN
6
BIPOFF
10
CS
DGND
DB11–DB4
4
14
26–19
DB3, DB2 18, 17
DB1 (R/L) 16
DB0 (HBE) 15
EOC
27
EOCEN
1
HBE (DB0) 15
OE
2
REFIN
9
REFOUT
8
R/L (DB1) 16
SC
3
SYNC
13
VCC
11
VEE
5
VDD
28
12/8
12
No Connect
11
P
10
AI
15
AI
6
DI
23
P
40, 39, 37, 36, DO
35, 34, 33, 31
30, 27
DO
26
DO
25
DO
42
DO
1
DI
25
DI
3
DI
14
AI
12
AO
26
DI
5
DI
21
DI
17
P
8
P
43
P
19
DI
2, 4, 7, 9, 13,
16, 18, 20, 22,
24, 28, 29, 32,
38, 41, 44
Analog Ground. This is the ground return for AIN only.
Analog Signal Input.
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary
output coding. Connect to REFOUT through 50 Ω resistor for ± 5 V input bipolar mode
and twos complement binary output coding. See Figures 7 and 8.
Chip Select. Active LOW.
Digital Ground
Data Bits 11 through 4. In 12-bit format (see 12/8 pin), these pins provide the upper 8 bits
of data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/L pin).
Active HIGH.
Data Bits 3 and 2. In 12-bit format, these pins provide Data Bit 3 and Data Bit 2.
Active HIGH. In 8-bit format they are undefined and should be tied to VDD.
In 12-bit format, Data Bit 1. Active HIGH.
In 12-bit format, Data Bit 0. Active HIGH.
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the
conversion is finished. In asynchronous mode, EOC is an open drain output and
requires an external 3 kΩ pull-up resistor. See EOCEN and SYNC pins for information
on EOC gating.
End-Of-Convert Enable. Enables EOC pin. Active LOW.
In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte.
Output Enable. The falling edge of OE enables DB11–DB0 in 12-bit format and
DB11–DB4 in 8-bit format. Gated with CS. Active LOW.
Reference Input. +5 V input gives 10 V full-scale range.
+5 V Reference Output. Tied to REFIN through 50 Ω resistor for normal operation.
In 8-bit format, Right/Left justified. Sets alignment of 12-bit result within 16-bit field.
Tied to VDD for right-justified output and tied to DGND for left-justified output.
Start Convert. Active LOW. See SYNC pin for gating.
SYNC Control. If tied to VDD (synchronous mode), SC, EOC and EOCEN are gated
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS,
and EOC is an open drain output. EOC requires an external 3 kΩ pull-up resistor in
asynchronous mode.
+12 V Analog Power.
–12 V Analog Power.
+5 V Digital Power.
Twelve/eight-bit format. If tied HIGH, sets output format to 12-bit parallel. If tied
LOW, sets output format to 8-bit multiplexed.
These pins are unused and should be connected to DGND or VDD.
Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers; P = Power.
DIP PACKAGE
PIN CONFIGURATIONS
JLCC PACKAGE
EOCEN 1
OE 2
28 VDD
27 EOC
SC 3
26 DB11
CS 4
25 DB10
VEE 5
24 DB9
AIN 6
AGND 7
REFOUT 8
REFIN 9
23 DB8
AD678 22 DB7
TOP VIEW
(Not to Scale) 21 DB6
20 DB5
BIPOFF 10
19 DB4
VCC 11
12/8 12
18 DB3
17 DB2
SYNC 13
16 DB1 (R/L)
DGND 14
15 DB0 (HBE)
–6–
NC
VEE
NC
AIN
AGND
REFOUT
NC
REFIN
BIPOFF
NC
VCC
6 5 4 3 2 44 43 42 41 40
7
PIN 1
39
IDENTIFIER
8
38
9
37
10
36
11
AD678
35
12
TOP VIEW
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
DB10
NC
DB9
DB8
DB7
DB6
DB5
NC
DB4
DB3
NC
NC = NO CONNECT
REV. C
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