MT88E39 Ver la hoja de datos (PDF) - Mitel Networks

Número de pieza

componentes Descripción

Fabricante

MT88E39

Calling Number Identification Circuit

Mitel Networks 

MT88E39

Advance Information

IN+ 1

IN- 2

GS 3

VRef 4

CAP 5

OSC1 6

OSC2 7

VSS 8

16 VDD

15 IC**

14 MODE*

13 PWDN

12 CD

11 DR

10 DATA

9 DCLK

16 PIN SOIC

* Was IC1 in MT88E41

** Was IC2 in MT88E41

Pin Description

Figure 2 - Pin Connections

Pin # Name

Description

1

IN+ Non-inverting Op-Amp (Input).

2

IN- Inverting Op-Amp (Input).

3

GS Gain Select (Output). Gives access to op-amp output for connection of feedback resistor.

4

VRef Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs.

5

CAP Capacitor. Connect a 0.1µF capacitor to VSS.

6 OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external

clocking source.

7 OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin

should be left open.

8

VSS Power supply ground.

9 DCLK 3-wire FSK Interface: Data Clock (CMOS Output/Schmitt Input). In mode 0 (MT88E41

compatible mode - when the MODE pin is logic low) this is a CMOS output which denotes the

nominal mid-point of a FSK data bit.

In mode 1 (when the MODE pin is logic high) this is a Schmitt trigger input used to shift the

FSK data byte out to the DATA pin.

10 DATA 3-wire FSK Interface: Data (CMOS Output). In mode 0 (MT88E41 compatible mode - when

the MODE pin is logic low) the FSK serial bit stream is output to DATA as demodulated. Mark

frequency corresponds to logical 1. Space frequency corresponds to logical 0.

In mode 1 (when the MODE pin is logic high) the start and stop bits are stripped off and only

the data byte is stored in a 1 byte buffer. At the end of each word signalled by the DR pin, the

microcontroller should shift the byte out to DATA pin by applying 8 read pulses at the DCLK pin.

11

DR 3-wire FSK Interface: Data Ready (Open Drain/CMOS Output). Active low. In mode 0

(MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. In

mode 1 (when the MODE pin is logic high) this is a CMOS output.

This pin denotes the end of a word. Typically, DR is used to interrupt the microcontroller. It is

normally hi-Z or high (modes 0 and 1 respectively) and goes low for half a bit time at the end of

a word. But in mode 1 if DCLK begins during DR low, the first rising edge of the DCLK input

will return DR to high. This feature allows an interrupt requested by DR to be cleared upon

reading the first DATA bit.

12

CD Carrier Detect (Open Drain/CMOS Output). Active low. In mode 0 (MT88E41 compatible

mode - when the MODE pin is logic low) this is an open drain output. In mode 1 (when the

MODE pin is logic high) this is a CMOS output.

A logic low indicates that a carrier has been present for a specified time on the line. A time

hysteresis is provided to allow for momentary discontinuity of carrier. The demodulated FSK

data is inhibited until the carrier has been detected.

13 PWDN Power Down (Schmitt Input). Active high. Powers down the device including the input

op-amp and the oscillator. Must be low for operation.

5-2

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