SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

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componentes Descripción

Fabricante

SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

FUNCTIONAL DESCRIPTION

Receive path

Receive Link Interface

For data input, two different data types, with selectable input active polarity sense, are

supported:

- Dual rail data (PCM[+], PCM[-]) at ports DRA, DRB received from a Line Interface

Unit.

- Unipolar data at port OPIN (PCM 30) received from a fibre optical Interface.

Latching of data is carried out using the falling edge of the Receive route Clock

(RCLK, 2048 kHz) recovered from the PCM receive data stream. Dual rail data is

subsequently converted into a single rail, unipolar bit stream. The HDB3 line code

is used along with Double Violation Detection or Extended Code Violation Detection

(selectable). These errors increment the Code Violation Counter.

When using the unipolar input mode, the decoder is by-passed and no code violation

will be detected.

Additionally, the receive Link Interface comprises the alarm detection for AIS (Alarm

Indication Signal: unframed bit stream with constant logical ‘one’) and NOS (No

Signal: Input signal with insufficient bit rate or insufficient density of ones).

The single rail bit stream is then processed by the Receiver.

Receiver

The following functions are performed:

- Synchronization of pulse frame

- Synchronization of CRC4 multi-frame

- Error Indication when pulse frame synchronization is lost. In this case, AIS is sent to

the system side. If the receiver is in transparent mode, AIS is suppressed.

- Initiating and controlling of re-synchronization after loss of synchronization. This may

be carried out automatically by the SA9101, or under user control via the microprocessor

interface.

- Detection of Remote Alarm Indication from the incoming data stream.

- Separation of service bits and data link bits. This information is stored in special status

registers.

- Generation of control signals to synchronize the CRC checker, the parity generator,

and the Receive Speech Memory control unit.

If the multi-frame format is selected, CRC checking of the Incoming data stream is

done by generating check bits for a CRC submultiframe according to the CRC 4

procedure (PCM30, refer to CCITT Rec. G704). These bits are compared with those

check bits that are received during the next CRC sub-multiframe. If there is a

mismatch, the CRC error counter will be incremented. This 8-bit counter (default) can

be extended to 10-bit length, by writing to the control registers.

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