SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

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Fabricante

SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

Clock Generator

Signal

Pin

SCLK

24

RFSPQ

5

SYPQ

28

Input/Output/Bidirect

I

O

I

Function

System Clock f=4,096 MHz/8,192MHz

Receive Frame Pulse

Frequency:

8 kHz

Duration: 488 ns

If loss of synchronisation, the line frame

pulse is inhibited

Synchronous Pulse

Defines start of frame for System internal

data, together with the programmed offset

values of transmit and receive counter.

Pulse width: >244 ns

Period: Multiples of 125µs

DIU Controller

Signal

Pin

D0 - D7 7 - 14

A0 - A3 16 - 19

Input/Output/Bidirect

B

I

CEQ

22

I

WRQ

21

I

RDQ

20

I

COS

23

I

XREQ

36

O

RREQ

37

O

AINT

3

O

ACKNLQ 32

I

Function

Bidirectional 8 bit data-bus

Address lines for SA9101 internal

registers

Chip enable input

Write enable input

Read enable input

Carrier out of service input.

SA9101 sends AIS to PCM30 interface

if input is at “1”

Transmit DMA interrupt request

Receive DMA interrupt request

Alarm interrupt request

DMA Acknowledge (Active Low)

(Not used when CR6B6 = 0. If not used

then pin must be fixed to VDD.) If access to

internal TS16 signalling stacks is enabled

this input acts as an "access enable" to the

internal stacks (CRAB0-7 for T and

X

SR7B0-7 for RX) in conjunction with a

read/write command without the need of

generating the chip enable signal at CEQ.

In this case it is to be connected to the

acknowledge output of the DMA controller.

sames

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