SA9101 Ver la hoja de datos (PDF) - South African Micro Electronic Systems

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SA9101

PCM FRAME ALIGNER

South African Micro Electronic Systems 

SA9101

Receive Speech Memory

The speech memory is organized as a two-frame elastic buffer with a size of 64 x 9 bit

(8-bit channel data plus one parity bit).

The functions are:

- Compensation of Input wander and jitter. Maximum wander amplitude (peak-to-

peak) = 190 UI (1UI = 488 nS)

- Frame alignment between system frame and receive route frame

- Reporting and controlling of slips

Controlled by special signals generated by the Receiver, the unipolar bit stream is

converted into bit-parallel, channel-serial data which is circularly written to the speech

memory. At the same time, a parity signal is generated over each channel and also

stored in the speech memory.

Reading of stored data is controlled by the System Clock (SCLK) and the Synchronization

Pulse (SYPQ) in conjunction with the programmed offset values for the Receive timeslot/

Clock slot Counters. After conversion into a serial data stream and parity checking

(errors are reported via the status registers), the data is given out via port DRO. Channel

parity information is output at port CHPAR with selectable parity type (odd or even). Two

bit rates (2048/4096 kbps) are selectable via the microprocessor interface.

Figure 1.0: The Receive Speech Memory as circularly organized memory

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