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T8110

Ambassador® T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine

Agere -> LSI Corporation 

Data Sheet

May 2001

Ambassador T8110 PCI-Based H.100/H.110 Switch

and Packet Payload Engine

Contents

Table of Contents (continued)

Page

6.1.10 Watchdog EN Register .................................................................................................................... 53

6.1.11 Failsafe Control Registers ................................................................................................................ 54

6.1.12 External Buffers—Descriptor Table Base Address .......................................................................... 55

6.2 Error and Status Registers ........................................................................................................................... 55

6.2.1 Clock Errors ..................................................................................................................................... 56

6.2.1.1 Transient Clock Errors Registers ......................................................................................... 56

6.2.1.2 Latched Clock Error Register .............................................................................................. 57

6.2.2 System Status .................................................................................................................................. 58

6.2.3 Clock Fallback Status Register ........................................................................................................ 58

6.2.4 PLL and Switching Status Register ..................................................................................................58

6.2.5 System Errors Register .................................................................................................................... 59

6.2.6 Device Identification Registers .........................................................................................................60

6.2.7 Miscellaneous Status ....................................................................................................................... 61

7 Clock Architecture ...............................................................................................................................................62

7.1 Clock Input Control Registers ....................................................................................................................... 63

7.1.1 Main Input Selector Register ............................................................................................................ 63

7.1.2 Main Divider Register ....................................................................................................................... 64

7.1.3 Analog PLL1 (APLL1) Input Selector Register ................................................................................. 64

7.1.4 APLL1 Rate Register ....................................................................................................................... 65

7.1.5 Main Inversion Select Register ........................................................................................................ 65

7.1.6 Resource Divider Register ............................................................................................................... 66

7.1.7 Analog PLL2 (APLL2) Rate Register ............................................................................................... 66

7.1.8 LREF Input Select Registers ............................................................................................................ 67

7.1.9 DPLL1 Input Selector ....................................................................................................................... 68

7.1.9.1 DPLL1 Rate Register ........................................................................................................... 68

7.1.10 DPLL2 Input Selector ....................................................................................................................... 69

7.1.10.1 DPLL2 Rate Register ........................................................................................................... 69

7.1.11 NETREF1 Registers ........................................................................................................................ 70

7.1.12 NETREF2 Registers ........................................................................................................................ 71

7.2 Clock Output Control Registers .................................................................................................................... 72

7.2.1 Master Output Enables Register ...................................................................................................... 72

7.2.2 Clock Output Format Registers ........................................................................................................ 74

7.2.3 TCLK and L_SCx Select Registers ..................................................................................................74

7.3 Clock Register Access .................................................................................................................................. 76

7.4 Clock Circuit Operation—APLL1 .................................................................................................................. 76

7.4.1 Main Clock Selection, Bit Clock, and Frame ....................................................................................76

7.4.1.1 Watchdog Timers ................................................................................................................ 77

7.4.1.2 Frame Center Sampling ...................................................................................................... 78

7.4.2 Main and Resource Dividers ............................................................................................................ 78

7.4.3 DPLL1 .............................................................................................................................................. 79

7.4.4 Reference Selector .......................................................................................................................... 79

7.4.5 Internal Clock Generation ................................................................................................................ 79

7.4.5.1 Phase Alignment ................................................................................................................. 80

7.5 Clock Circuit Operation, APLL2 .................................................................................................................... 81

7.5.1 DPLL2 .............................................................................................................................................. 81

7.6 Clock Circuit Operation, CT_NETREF Generation ....................................................................................... 81

7.6.1 NETREF Source Select ................................................................................................................... 81

7.6.2 NETREF Divider .............................................................................................................................. 81

7.7 Clock Circuit Operation—Fallback and Failsafe ...........................................................................................82

Agere Systems Inc.

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