W83629D Ver la hoja de datos (PDF) - Winbond

Número de pieza

componentes Descripción

Fabricante

W83629D

PCI TO ISA BRIDGE SET

Winbond 

W83628F & W83629D

7. PIN DESCRIPTION

Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.

I/O12t

- TTL level bi-directional pin with 12 mA source-sink capability

I/O24t

- TTL level bi-directional pin with 24 mA source-sink capability

I/O12tp3 - 3.3V TTL level bi-directional pin with 12 mA source-sink capability

I/O24tp3 - 3.3V TTL level bi-directional pin with 24 mA source-sink capability

I/OD12t

- TTL level bi-directional pin open drain output with 12 mA sink capability

I/O24t

- TTL level bi-directional pin with 24 mA source-sink capability

OUT12t

- TTL level output pin with 12 mA source-sink capability

OUT24t

- TTL level output pin with 24 mA source-sink capability

OUT12tp3 - 3.3V TTL level output pin with 12 mA source-sink capability

OUT24tp3 - 3.3V TTL level output pin with 24 mA source-sink capability

OD12

- Open-drain output pin with 12 mA sink capability

OD24

- Open-drain output pin with 24 mA sink capability

INcs

- CMOS level Schmitt-trigger input pin

INt

- TTL level input pin

INtd

- TTL level input pin with internal pull down resistor

INts

- TTL level Schmitt-trigger input pin

INtsp3

- 3.3V TTL level Schmitt-trigger input pin

7.1 W83628F PIN DESCRIPTION

7.1.1 PCI Interface

SYMBOL

AD[31:0]

C/BE[3:0]#

PCICLK

PCLK_OUT

PIN

19-26

30-37

52-59

61-63

66-70

28,45

51,60

47

48

I/O

I/O24tp3

I/O24tp3

INt

OUT12t

FUNCTION

PCI Bus Address and Data Signals. The standard PCI address

and data lines. Address is driven with FRAME# assertion, data is

driven or received in following clocks.

PCI Bus Command and Byte Enables. During the address

phase of a transaction C/BE[3:0]# define the bus command.

During the data phase C/BE[3:0]# are used as Byte Enables.

PCI Bus System Clock. PCICLK provides timing for all

transactions on the PCI bus. All other PCI signals are sampled

on the rising edge of PCICLK, and all timing parameters are

defined with respect to this edge.

PCI Bus System Clock DPLL Output. The PCLK_OUT can

reduce the PCICLK Loading and it produced from internal DPLL.

-8-

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