74F378SJ(1999) Ver la hoja de datos (PDF) - Fairchild Semiconductor
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74F378SJ Datasheet PDF : 6 Pages
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April 1988
Revised August 1999
74F378
Parallel D-Type Register with Enable
General Description
The 74F378 is a 6-bit register with a buffered common
Enable. This device is similar to the 74F174, but with com-
mon Enable rather than common Master Reset.
Features
s 6-bit high-speed parallel register
s Positive edge-triggered D-type inputs
s Fully buffered common clock and enable inputs
s Input clamp diodes limit high-speed termination effects
s Full TTL and CMOS compatible
Ordering Code:
Order Number Package Number
Package Description
74F378SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F378SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F378PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009526
www.fairchildsemi.com
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