ORT82G5 Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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ORT82G5
Agere -> LSI Corporation
ORT82G5 Datasheet PDF : 92 Pages
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ORCA ORT82G5 FPSC Eight-Channel
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
Preliminary Data Sheet
July 2001
Table of Contents
Contents
Page Contents
Page
Introduction ..................................................................1
Embedded Function Features .....................................4
Intellectual Property Features......................................4
Programmable Features..............................................5
Programmable Logic System Features .......................6
Description...................................................................7
What Is an FPSC? ....................................................7
FPSC Overview .........................................................7
FPSC Gate Counting ................................................7
FPGA/Embedded Core Interface ..............................7
ORCA Foundry 2000 Development System .............7
FPSC Design Kit .......................................................8
FPGA Logic Overview ...............................................8
PLC Logic ..................................................................8
Programmable I/O .....................................................9
Routing ......................................................................9
System-Level Features..............................................10
Microprocessor Interface .........................................10
System Bus .............................................................10
Phase-Locked Loops ..............................................10
Embedded Block RAM ............................................10
Configuration ...........................................................11
Additional Information .............................................11
ORT82G5 Overview ..................................................11
Device Layout .........................................................11
Backplane Transceiver Interface .............................11
ORT82G5 Overview (continued) ...............................12
Serializer and Deserializer (SERDES) ....................14
MUX/DeMUX Block .................................................14
Multichannel Alignment FIFOs ................................14
XAUI or Fibre-Channel Link State Machine ............14
Dual Port RAMs ......................................................14
FPGA Interface .......................................................15
FPSC Configuration ................................................15
Backplane Transceiver Core Detailed Description ....15
SERDES .................................................................15
SERDES Transmit Path (FPGA Æ Backplane) ......18
Transmit Preemphasis and Amplitude Control ........19
SERDES Receive Path (Backplane Æ FPGA) .......19
8b/10b Encoding/Decoding .....................................21
SERDES Transmit and Receive PLLs ................... 21
Reference Clock ..................................................... 21
Byte Alignment ....................................................... 22
Link State Machines ............................................... 22
XAUI Link Synchronization Function ...................... 23
MUX/DeMUX Block ................................................ 25
Multichannel Alignment (Backplane Æ FPGA) ....... 27
Alignment Sequence .............................................. 29
Loopback Modes .................................................... 32
High-Speed Serial Loopback .................................. 32
Parallel Loopback at the SERDES Boundary ......... 33
Parallel Loopback at MUX/DeMUX Boundary
Excluding SERDES ............................................... 33
ASB Memory Blocks ............................................... 34
Memory Map............................................................. 36
Definition of Register Types ................................... 36
Absolute Maximum Ratings...................................... 54
Recommended Operating Conditions ...................... 54
HSI Electrical and Timing Characteristics ................ 54
Pin Information ......................................................... 57
Power Supplies for ORT82G5 ................................ 63
Recommended Power Supply Connections ........... 64
Recommended Power Supply Filtering Scheme .... 64
Package Pinouts .................................................... 69
Pin Information ......................................................... 70
Package Thermal Characteristics
Summary.................................................................. 87
ΘJA ......................................................................... 87
ψJC ........................................................................ 87
ΘJC ........................................................................ 87
ΘJB ........................................................................ 87
FPSC Maximum Junction Temperature ................. 87
Package Thermal Characteristics............................. 88
Package Coplanarity ................................................ 88
Package Parasitics ................................................... 88
Package Outline Diagrams....................................... 89
Terms and Definitions ............................................ 89
680-Pin PBGAM ..................................................... 90
Hardware Ordering Information ................................ 91
Software Ordering Information ................................. 91
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Agere Systems Inc.
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