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OR3LP26B

ORCA® OR3LP26B Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Agere -> LSI Corporation 

ORCA OR3LP26B FPSC

Embedded Master/Target PCI Interface

Data Sheet

March 2000

Table of Contents (continued)

Contents

Page Contents

Page

Table 13. Dual-Port FIFO Packing/Unpacking, Case 1,

PCI Side ...................................................................... 33

Table 14. Dual-Port FIFO Packing/Unpacking, Case 1,

FPGA Side .................................................................. 33

Table 15. Dual-Port FIFO Packing/Unpacking, Case 2,

PCI Side ....................................................................... 33

Table 16. Dual-Port FIFO Packing/Unpacking, Case 2,

FPGA Side .................................................................. 34

Table 17. Index to State Sequence Tables ..................... 35

Table 18. Dual-Port Master Write .................................. 41

Table 19. Dual-Port Master Read, 64-Bit Address

Supplied ....................................................................... 48

Table 20. Dual-Port Master Read, 32-Bit Address

Supplied ...................................................................... 48

Table 21. Dual-Port Target Write ................................... 57

Table 22. Dual-Port Target Read ................................... 69

Table 23. Embedded Core/FPGA Interface Signals ....... 70

Table 24. OR3LP26B FPGA/PCI Core Interface Signal

Locations...................................................................... 76

Table 25. Bit Definitions on FPGA/PCI Core Interface ... 79

Table 26. Address Cycle Sequences for Various

Operations ................................................................... 82

Table 27. PCI Core Options Settable via FPGA

Configuration RAM Bits ................................................ 83

Table 28. Quad-Port FIFO Packing/Unpacking, Case 1,

PCI Side ....................................................................... 84

Table 29. Dual-Port FIFO Packing/Unpacking, Case 1,

FPGA Side .................................................................. 84

Table 30. Quad-Port FIFO Packing/Unpacking, Case 1,

PCI Side ...................................................................... 85

Table 31. Quad-Port FIFO Packing/Unpacking,

Case 1, FPGA Side...................................................... 85

Table 32. Quad-Port FIFO Packing/Unpacking, Case 2,

PCI Side ....................................................................... 85

Table 33. Quad-Port FIFO Packing/Unpacking, Case 1,

FPGA Side ................................................................... 85

Table 34. Holding Registers, Examples of Typical

Operation ..................................................................... 86

Table 35. Index to State Sequence Tables ..................... 87

Table 36. Quad-Port Master Write ................................. 93

Table 37. Quad-Port Master Read, Duplicate Burst

Length and 16-Bit Address........................................... 100

Table 38. Quad-Port Master Read, Specified Burst

Length and 64-Bit Address .......................................... 100

Table 39. Quad-Port Target Write .................................. 109

Table 40. Quad-Port Target Read................................... 122

Table 41. Configuration Space Layout............................ 123

Table 42. Configuration Space Assignment ................... 124

Table 43. Configuration Frame Format and Contents .... 131

Table 44. Configuration Frame Size ............................... 132

Table 45. Configuration Modes....................................... 132

Table 46. Absolute Maximum Ratings ............................ 133

Table 47. Recommended Operating Conditions............. 134

Table 48. Electrical Characteristics ................................ 135

Table 49. Derating for Commercial Devices

(I/O Supply VDD) ......................................................... 136

4

Table 50. .........................................................................Der-

ating for Commercial Devices (I/O Supply VDD2) ........136

Table 51. ExpressCLK (ECLK) and Fast Clock (fclk)

TimingCharacteristics ...................................................137

Table 52. General-Purpose Clock Timing

Characteristics (Internally Generated Clock) ................138

Table 53. OR3LP26B ExpressCLK to Output

Delay (Pin-to-Pin) .........................................................138

Table 54. OR3LP26B Fast Clock (fclk) to Output

Delay (Pin-to-Pin) .........................................................139

Table 55. OR3LP26B General System Clock (SCLK)

to Output Delay (Pin-to-Pin)..........................................140

Table 56. OR3LP26B Input to ExpressCLK (ECLK)

Fast-Capture Setup/Hold Time (Pin-to-Pin) ..................141

Table 57. OR3LP26B Input to Fast Clock

Setup/Hold Time (Pin-to-Pin)........................................142

Table 58. OR3LP26B Input to General System

Clock (SCLK) Setup/Hold Time (Pin-to-Pin) .................143

Table 59. OR3LP26B PCI and FPGA Interface Clock

Operation Frequencies .................................................143

Table 60. OR3LP26B FPGA to PCI, and PCI to FPGA,

Combinatorial Path Delays ...........................................144

Table 61. OR3LP26B FPGA Side Interface

Combinatorial Path Delay Signals ................................144

Table 62. OR3LP26B Interbuf Delays .............................145

Table 63. OR3LP26B FPGA Side Interface Clock to

Output Delays, pciclk Synchronous Signals .................145

Table 64. OR3LP26B FPGA Side Interface Clock to

Output Delays, fclk Synchronous Signals .....................146

Table 65. OR3LP26B FPGA Side Interface Input

Setup Delays, pciclk Synchronous Signals...................147

Table 66. OR3LP26B FPGA Side Interface Input

Setup Delays, fclk Synchronous Signals ......................147

Table 67. PCI Core Internal Power Dissapation .............150

Table 68. FPGA Common-Function Pin Descriptions.....151

Table 69. ORCA OR3LP26B I/Os Summary ..................154

Table 70. Pinout Information ..........................................155

Table 71. ORCA OR3LP26B Plastic Package Thermal

Guidelines ..................................................................... 178

Table 72. Package Coplanarity .......................................179

Table 73. Package Parasitics ..........................................180

Table 74. Voltage Options ...............................................184

Table 75. Package Options .............................................184

Table 76. ORCA Series 3+ Package Matrix ....................184

Table 77. Embedded Core Type......................................184

Table 78. FPSC Base Array ............................................184

Lucent Technologies Inc.

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