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MSM66P201 Ver la hoja de datos (PDF) - Oki Electric Industry

Número de pieza
componentes Descripción
Fabricante
MSM66P201
OKI
Oki Electric Industry OKI
MSM66P201 Datasheet PDF : 30 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
¡ Semiconductor
MSM66201/66P201/66207/66P207
PIN DESCRIPTION (Continued)
Symbol
RESOUT
ALE
PSEN
RD
WR
READY
EA
FLT
RES
OSC0
OSC1
NMI
VREF
AGND
VDD
GND
Type
O
O
O
O
O
I
I
I
I
I
O
I
Description
Outputs "H" level in the case of internal reset.
Reset to"L" level by program.
Address Latch Enable:
The timing pulse to latch the lower 8 bits of the address
output from port 0 when the CPU accesses the external
memory.
Program Strobe Enable: The strobe pulse to fetch to external program
memory.
Output strobe activated during a bus read cycle.
Used to enable data onto the bus from the external data memory.
Output strobe during a bus write cycle.
Used as write strobe to external data memory.
Used when the CPU accesses low-speed peripherals.
Normaly set to "H" level.
If set to "L" level, the CPU fetches the code from external program memory.
If FLT is "H" level, ALE, WR, RD, PSEN are set to "H" level when reset.
If FLT is set to "L", ALE, WR, RD, PSEN are set to floating level when reset.
RESET input pin.
Basic clock oscillation pin.
Basic clock oscillation pin.
Non-maskable interrupt input pin (falling edge).
Reference voltage input pin for A/D converter.
Ground for A/D converter.
System power supply.
Ground.
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