AD8803 Ver la hoja de datos (PDF) - Analog Devices
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AD8803 Datasheet PDF : 16 Pages
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AD8801/AD8803–SPECIFICATIONS (VDD = +3 V ؎ 10% or +5 V ؎ 10%, VREFH = +VDD, VREFL = 0 V, –40؇C
≤ TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol Conditions
Min Typ1 Max
Units
STATIC ACCURACY
Specifications Apply to All DACs
Resolution
N
8
Integral Nonlinearity Error
INL
–1.5
Differential Nonlinearity
DNL
Guaranteed Monotonic
–1
Full-Scale Error
GFSE
–4
Zero-Code Error
VZSE
–0.5
DAC Output Resistance
ROUT
3
Output Resistance Match
∆R/RO
REFERENCE INPUT
Voltage Range2
Input Resistance
Reference Input Capacitance3
VREFH
0
VREFL
Pin Available on AD8803 Only
0
RREFH
Digital Inputs = 55H, VREFH = VDD
CREF0
Digital Inputs All Zeros
CREF1
Digital Inputs All Ones
DIGITAL INPUTS
Logic High
VIH
VDD = +5 V
2.4
Logic Low
VIL
VDD = +5 V
Logic High
VIH
VDD = +3 V
2.1
Logic Low
VIL
VDD = +3 V
Input Current
Input Capacitance3
IIL
VIN = 0 V or +5 V
CIL
POWER SUPPLIES4
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Shutdown Current
Power Dissipation
Power Supply Sensitivity
Power Supply Sensitivity
VDD Range
2.7
IDD
VIH = VDD or VIL = 0 V
IDD
VIH = 2.4 V or VIL = 0.8 V, VDD= +5.5 V
IREFH
SHDN = 0
PDISS
VIH = VDD or VIL = 0 V, VDD = +5.5 V
PSRR
VDD = 5 V ± 10%, VREFH = +4.5 V
PSRR
VDD = 3 V ± 10%, VREFH = +2.7 V
DYNAMIC PERFORMANCE3
VOUT Settling Time (Positive or Negative) tS
Crosstalk
CT
± 1/2 LSB Error Band
See Note 5, f = 100 kHz
± 1/2 +1.5
± 1/4 +1
–2.8 +0.5
± 0.1 +0.5
5
8
1
VDD
VDD
2
25
25
0.8
0.6
±1
5
0.01
1
0.01
0.001
0.01
5.5
5
4
5
27.5
0.002
0.6
50
Bits
LSB
LSB
LSB
LSB
kΩ
%
V
V
kΩ
pF
pF
V
V
V
V
µA
pF
V
µA
mA
µA
µW
%/%
%/%
µs
dB
SWITCHING CHARACTERISTICS3, 6
Input Clock Pulse Width
tCH, tCL
Clock Level High or Low
15
ns
Data Setup Time
tDS
5
ns
Data Hold Time
tDH
5
ns
CS Setup Time
tCSS
10
ns
CS High Pulse Width
tCSW
10
ns
Reset Pulse Width
tRS
60
ns
CLK Rise to CS Rise Hold Time
tCSH
15
ns
CS Rise to Next Rising Clock
tCS1
10
ns
NOTES
1Typical values represent average readings measured at +25 °C.
2VREFH can be any value between GND and VDD, for the AD8803 VREFL can be any value between GND and VDD.
3Guaranteed by design and not subject to production test.
4Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).
5Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change.
6See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
–2–
REV. A
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