HMP8156ACN Ver la hoja de datos (PDF) - Intersil

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HMP8156ACN

NTSC/PAL Encoders

Intersil 

HMP8154, HMP8156A

Host Interfaces

Reset

The HMP8154/HMP8156A resets to its default operating

mode on power up, when the reset pin is asserted for at least

four CLK cycles, or when the software reset bit of the host

control register is set. During the reset cycle, the encoder

returns its internal registers to their reset state and

deactivates the I2C interface.

I2C Interface

The HMP8154/HMP8156A provides a standard I2C interface

and supports fast-mode (up to 400 Kbps) transfers. The

device acts as a slave for receiving and transmitting data

only. It will not respond to general calls or initiate a transfer.

The encoder’s slave address is either 0100 000xB when the

SA input pin is low or 0100 001xB when it is high. (The ‘x’ bit

in the address is the I2C read flag.)

The I2C interface consists of the SDA and SCL pins. When

the interface is not active, SCL and SDA must be pulled high

using external 4-6kΩ pull-up resistors. The I2C clock and

data timing is shown in Figures 20 and 21.

During I2C write cycles, the first data byte after the slave

address specifies the sub address, and is written into the

address register. Only the seven LSBs of the subaddress are

used; the MSB is ignored. Any remaining data bytes in the

I2C write cycle are written to the control registers, beginning

with the register specified by the address register. The 7-bit

address register is incremented after each data byte in the

I2C write cycle. Data written to reserved bits within registers

or reserved registers is ignored.

During I2C read cycles, data from the control register

specified by the address register is output. The address

register is incremented after each data byte in the I2C read

cycle. Reserved bits within registers return a value of “0”.

Reserved registers return a value of 00H.

The HMP8154/HMP8156A’s operating modes are

determined by the contents of its internal registers which are

accessed via the I2C interface. All internal registers may be

written or read by the host processor at any time. However,

some of the bits and words are read only or reserved and

data written to these bits is ignored.

Table 10 lists the HMP8154/HMP8156A’s internal registers.

Their bit descriptions are listed in Tables 11-30.

TABLE 10. CONTROL REGISTER NAMES

SUB ADDRESS

(HEX)

CONTROL REGISTER

RESET

CONDITION

00

01

02

03

04

05

06

07-0E

0F

10

11

12

13

14-1F

20

21

22

23

24

25

26

27

28-2F

30-7F

Product ID

54H

Output Format

00H

Input Format

06H

Video Processing

A0H

Timing I/O 1

00H

Timing I/O 2

00H

Aux Data Enable

00H

Reserved

-

Host Control

0CH

Closed Caption_21A

80H

Closed Caption_21B

80H

Closed Caption_284A

80H

Closed Caption_284B

80H

Reserved

-

Start H_Blank Low

4AH

Start H_Blank High

03H

End H_Blank

7AH

Start V_Blank Low

03H

Start V_Blank High

01H

End V_Blank

13H

Field Control 1

80H

Field Control 2

00H

Reserved

-

Test and Unused

-

SDA

SCL

S

1-7

8

9

1-7

8

9

DATA WRITE

START

CONDITION

ADDRESS

R/W

ACK

DATA

FIGURE 20. I2C SERIAL TIMING FLOW

ACK

S

DATA READ

CHIP ADDR

0x40 OR

0x42

A SUB ADDR

A

DATA

REGISTER

POINTED

TO BY

SUBADDR

A

DATA

AP

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

S CHIP ADDR A SUB ADDR A S CHIP ADDR A DATA

A DATA

NA P

0x40 OR

0x42

0x41 OR

0x43

REGISTER

POINTED

TO BY

SUBADDR

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

FIGURE 21. REGISTER WRITE PROGRAMMING FLOW

P

STOP

CONDITION

S = START CYCLE

P = STOP CYCLE

A = ACKNOWLEDGE

NA = NO ACKNOWLEDGE

FROM MASTER

FROM ENCODER

17

4343.4

November 4, 2005

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