HMP8156ACN Ver la hoja de datos (PDF) - Intersil

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componentes Descripción

Fabricante

HMP8156ACN

NTSC/PAL Encoders

Intersil 

HMP8154, HMP8156A

BIT

NUMBER

FUNCTION

7-0

Line 21 Caption

Data

(First Byte)

BIT

NUMBER

FUNCTION

7-0

Line 21 Caption

Data

(Second Byte)

BIT

NUMBER

FUNCTION

7-0

Line 284 Caption

Data

(First Byte)

BIT

NUMBER

FUNCTION

7-0

Line 284 Caption

Data

(Second Byte)

BIT

NUMBER

FUNCTION

7-0

Assert BLANK

Output Signal

(Horizontal)

BIT

NUMBER

FUNCTION

7-2

Reserved

1-0

Assert BLANK

Output Signal

(Horizontal)

TABLE 19. CLOSED CAPTION_21A DATA REGISTER

SUB ADDRESS = 10H

DESCRIPTION

This register is cascaded with the closed caption_21B data register and they are read out se-

rially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A data

register is shifted out first.

RESET

STATE

80H

TABLE 20. CLOSED CAPTION_21B DATA REGISTER

SUB ADDRESS = 11H

DESCRIPTION

This register is cascaded with the closed caption_21A data register and they are read out se-

rially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A data

register is shifted out first.

RESET

STATE

80H

TABLE 21. CLOSED CAPTION_284A DATA REGISTER

SUB ADDRESS = 12H

DESCRIPTION

This register is cascaded with the closed caption_284B data register and they are read out se-

rially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the 284A

data register is shifted out first.

RESET

STATE

80H

TABLE 22. CLOSED CAPTION_284B DATA REGISTER

SUB ADDRESS = 13H

DESCRIPTION

This register is cascaded with the closed caption_284A data register and they are read out se-

rially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the 284A

data register is shifted out first.

RESET

STATE

80H

TABLE 23. START H_BLANK LOW REGISTER

SUB ADDRESS = 20H

DESCRIPTION

This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit

start_horizontal_blank register. It specifies the horizontal count (in 1X clock cycles) at which

to start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This

register is ignored unless BLANK is configured as an output.

RESET

STATE

4AH

TABLE 24. START H_BLANK HIGH REGISTER

SUB ADDRESS = 21H

DESCRIPTION

This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit

start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to

start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This reg-

ister is ignored unless BLANK is configured as an output.

RESET

STATE

000000B

11B

21

4343.4

November 4, 2005

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