BU1425AK Ver la hoja de datos (PDF) - ROHM Semiconductor

Número de pieza

componentes Descripción

Fabricante

BU1425AK

NTSC / PAL digital RGB encoder

ROHM Semiconductor 

Multimedia ICs

Pin No.

Pin name I / O

28

HSY

I/O

27

VSY

I/O

29

PIXCLK

O

32

INT

I

33

SLABEB

I

34

ADDH

I

35

VREF-C

I

37

COUT

O

8

Equivalent circuit

BU1425AK / BU1425AKV

Function

This is the horizontal synchronization

signal pin. Negative polarity Hsync

signals are input (when SLABEB =

LOW) or output (when SLABEB =

HIGH) here. This is also used as the

synchronization signal for fixing the

PIXCLK output phase.

Vertical synchronization signals (Vsync)

are input (when SLABEB = LOW) or

output (when SLABEB = HIGH) here.

The internal processing clock is divid-

ed in half and output. Data is read at

the point at which the edge of this

clock changes. This can also be used

as the clock for the OSD IC.

This pin switches between interlace

(when HIGH) and non-interlace (when

LOW) modes. This pin is effective in

both the VIDEO-CD and CD-G

modes.

This pin switches between the Master

(when HIGH) and Slave (when LOW)

modes. It is effective in the non-

interlace mode, and it switches bet-

ween – 0.5 lines (when LOW) and + 0.5

lines (when HIGH) for the number of

lines in an interlace field.

This is the reference voltage generator

circuit monitoring pin which deter-

mines the output amplitude (output cur-

rent for 1 LSB) of the DAC. A 0.01µF

capacitor should be attached between

this and pin 43 (AVDD).

This is the chrominance output pin for

the S pin.

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