SC9256 Ver la hoja de datos (PDF) - Silan Microelectronics
Número de pieza
componentes Descripción
Fabricante
SC9256 Datasheet PDF : 24 Pages
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Silan
Semiconductors
SC9256
Serial transfer format
The serial transfer format consists of 8 address bits and 24 data bits (Fig. 1). Addresses D0H~D3H are used.
Start
PERIOD t3
t4
End
t5
t6 t7
t1 t2
9 clock signal fall
CLOCK
DATA
t8
(*) (*) 0 0 1 0 1 1
LSB
MSB LSB
MSB
8 address bits
Fig.1
24 data bits
(24bit register)
• Serial data transfer
serial data are transferred in sync with the clock signal. In the idle state, the PERIOD, CLOCK and DATA pin
lines are all set to “H” level. When the period signal is at “L” level, the falling of the clock signal initiates serial
data transfer. Data transfer ceases when the period signal is set to “L” level when the clock signal is at “H” level.
Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time
the period signal is at “L” level.
Since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the
sending side to produce output in sync with the clock signal fall.
To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after
the 8 bit address is output but before the next clock signal falls.
Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before
the period signal rises. Therefore, the data pin must have an open-drain or tristate interface.
Note: 1. when power is turned on, some internal circuit have undefined states. To set internal circuit states,
execute a dummy data transfer before performing regular data transfer.
2. times t1~t8 have the following value:
t1≥1.0µs
t2≥1.0µs
t3≥0.3µs
t4≥0.3µs
t5≥0.3µs
t6≥1.0µs
t7≥1.0µs
t8≥0.3µs
3. Asterisks represent numbers taken from addresses, as in D*H.
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
REV: 1.0
8
2002.01.30.
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